STM32H747 with external NAND Flash and ECC hardware in MCU

[RMich.2]

Hi together

We use a STM32H747 MCU with an external NAND SLC Flash on the FMC bus.
In the reference manual in chapter "23.8.6 Computation of the error correction code (ECC) in NAND Flash memory" and some pages later in the description of the ECC register "ECC result registers (FMC_ECCR)" it is mentioned that a 1 bit error can be detected and corrected. We are aware of that, that is hamming.
But we don't know how the ECC is constructed. You cool ST guys cast that in silicon, but you didn't document it. You write at e.g. 256 byte size it is ECC[21:0] so 22 bits.

Now our questions:
- How is the data position and bit error position calculated?
- How is the division into even and odd parity?

According to the Ref. manual we don't know what you have cast into silicon and the description in the manual is not helpful.

Would you please provide us with a code example and describe the result of the STM32 hardware better?

There is code on the web, but we can't put software in devices that are sold by 100'000 pieces and we don't know how it works.

Thank you. :)

[FBL]

Hello @RMich.2

I am not sure if I got your questions, could you please develop more the use case? 

About the documentation, as mentioned in section ECC result registers (FMC_ECCR), when the CPU reads or writes data from the NAND flash memory, the ECC computation module automatically processes the data and generates a new set of parity bits. The CPU then reads the computed ECC value from the FMC_ECC registers and compares it with the parity value recorded in the spare area. The error correction code algorithm implemented in the FMC can perform 1-bit error correction and 2-bit error detection per page read from or written to the NAND Flash memory. It is based on the Hamming algorithm and consists in calculating the row and column parity.

I suggest taking a look to Using the high-density STM32F30xxD/E FMC peripheral to drive external memories

section 4.4 Error correction code computation for further details.

Hope this helps!

[Tesla DeLorean]

It's been probably a decade since I was dealing with ECC for NANDs, but I'm pretty sure ST's implementation a) does not correct, and b) is probably ill suited to MLC devices.

The ability to generate and check Reed-Solomon Syndrome bytes is actually a relatively uncomplicated task, in fact most memories over this last decade are capable of self generation and self checking, using codes that are sector/array appropriate. The *correction* is a more complicate task, usually requiring user side library code to manage and apply. Code for this is often manufacturer specific, and provided in a form usable by Linux / uBoot implementations.