STM32H745 timer master/slave

[GHolc.1]

I have timer 1 setup to PWM a wave form and timer 2 setup to PWM a different frequency wave form.  I need to restart timer 2 when an output compare match (CNT = CCR) on timer 1 occurs.  It appears that I can do this with master/slave configuration of the two timers but I am struggling with the reference manual explanation.  If I want to use timer 1 as the timer master and timer 2 as the timer slave, is it only timer 1 channel 1 (OC1) that I can use as the timer master? It looks like the reference guide, table 351 is telling me that when TIM2 is the slave and TIM1 is the master that I will need to be configuring for ITR0, but there is limited definition there for what the table means.  Any confirmation or tripping points would be appreciated, if there is a good app note that covers this, that would be appreciated a point to also.

[TDK]

Each timer has a single TRGO signal which can be hooked up to a bunch of things internally. You want this hooked up to OC1 or OC1REF on the master timer if you're using channel 1 as your PWM.

On the slave timer, set it up so that the timer resets when the TRGO signal occurs. Slave mode: Reset mode. and set the trigger source to the correct value. Probably ITR0 for a TIM1 master.

[waclawek.jan]

Start with reading the TIM chapter in RM. Skim through it first; it may \not make much sense at first reading, so you may want to re-read it, especially chapters you judge are relevant for your question. Also, read the related descriptions of the registers bits/bitfields, they are maybe even more instructive than the narrative.

What you need here is:

- set TIM1_CR2.MMS=0b100 to select OC1REF (i.e. output from the TIM1_CH1 comparator) as TRGO (trigger signal going out from timer), or 0b101..0b111 for OC2REF..OC4REF

- set TIM2_SMCR.TS to 0b000000 to select ITR0 as input trigger (TRGI). What ITR0 is is in the Table 351 you've mentioned TIMx internal trigger connection, so in TIM2, ITR0 is the trigger signal coming from TIM1. Would you need TIM2 to be triggered from a different timer, you would select it using different value in  TIM2_SMCR.TS (e.g. for TIM3 as trigger source you would look up table 351, that's ITR2, so you would set TIM2_SMCR.TS to 0b000010.) Note, that TIM2_SMCR.TS bitfield is not continuous.

- set TIM2_SMCR.SMS to 0b0100 for Reset mode (this bitfield is not continuous either).

That should be it.

There's a general timer overview appnote AN4013 and "timer cookbook" appnote AN4776, but I'm not quite sure how useful reading those may get.

Or you can forget everything I wrote above and just click in CubeMX, if that's your thing.

JW

[GHolc.1]

Thanks both of you, I reviewed both your your responses.  I was trying to use timer 1 channel 3 to synchronize timers, I moved to timer 1 channel 1.  My timers synchronize like needed when I setup TIM1_CR2 MMS bits to 011 (compare pulse) as long as I'm using channel 1.  So my problem is resolved.

I think my biggest barrier was exactly what OC1REF (or OC3REF) is and how it is controlled.  When I set my MMS bits to 100 (OC1REF), and have my SMCR setup for ITR0, it looks like my timer 2 resets exactly when timer 1 resets, and adjusting the channel 1 CCR (pulse length), or changing the pwm output polarity or idle state have no effect on when timer 2 resets, its always immediately after timer 1 resets.  Maybe that cookbook document explains OC1REF, I'll look that up.  Again, thanks, and my two timers master/slave are now doing exactly what I need.

[waclawek.jan]

Polarity and exact waveform of OCxRef depend on the mode selected in TIMx_CCMRx.OCxM (I've just noticed that in that picture, the incorrect register is mentioned, as OC1CE/OC1M are in TIMx_CCMR1 rather than TIMx_CCMR2). I need to review how do I use it in my programs, maybe I've never though about a combination you are using, PWM1 and PWM2 probably make a difference.

JW