2020-01-03 12:38 AM
Hi all,
my SDRAM setup seems to work EXCEPT that I have a strange behavior:
When I write any value (8, 16, 32 bit) to an address (example 0xd000004),
it in fact gets written to the address - 2, in this example 0xd0000002.
All written bytes are readably @0xd0000002.
Obviously I cannot see if the write-access has an offset of -2 or the read-access has an offset of +2.
Example:
uint16_t * pui = (uint16_t *)0xd0000004;
pui[0] = 0x1234;
if (pui[0] == 0x1234)
{
// Error! Do not come here!
}
if (pui[-1] == 0x1234])
{
// But I come here!
}
Everything else works fine, I have the LCD content mapped into the SDRAM. Everything works, but only if I write every value with an offset of +2.
Has anyone ever experienced something like this?
Maybe a problem with the SDRAM config?
Here is my configuration code:
hsdram1.Instance = FMC_SDRAM_DEVICE;
// tMem = 8.33ns
hsdram1.Init.SDBank = FMC_SDRAM_BANK2;
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3; // FMC_SDRAM_CAS_LATENCY_2;
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
/* SdramTiming */
// SDRAM Datenblatt: tMRD: 2 clocks
SdramTiming.LoadToActiveDelay = 2; // FMC_SDTRx.TMRD
// SDRAM Datenblatt: tXSR: 70 ns
SdramTiming.ExitSelfRefreshDelay = 9; // FMC_SDTRx.TXSR
// SDRAM Datenblatt: tRAS: 40-120 ns
SdramTiming.SelfRefreshTime = 15; // FMC_SDTRx.TRAS
// SDRAM Datenblatt: tRC: 70 ns
SdramTiming.RowCycleDelay = 9; // FMC_SDTRx.TRC
// SDRAM Datenblatt: tWR: 1 Clk + 7 ns
SdramTiming.WriteRecoveryTime = 2;// FMC_SDTRx.TWR
// SDRAM Datenblatt: tRP: 20 ns
SdramTiming.RPDelay = 3; // FMC_SDTRx.TRP
// SDRAM Datenblatt: tRCD: 20 ns
SdramTiming.RCDDelay = 3; // FMC_SDTRx.TRCD
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
{
Error_Handler( );
}
Any help would be highly appreciated!
regards
Louis
2020-01-03 05:23 AM
How is the FMC clock configured? (FMC clock selection, PLL values)
Is the I/O Compensation Cell enabled?
Can you verify that tMem is indeed 8.333 ns, i.e. SDCLK = 120 MHz ?
Try increasing the timing parameters one by one. Start with the read pipe delay, I vaguely remember having similar problems caused by this one being one too low.
2020-01-03 09:34 AM
Dear Berendi,
thank you for your afford!
I'm pretty sure that I have a SDCLK of 120 MHz (see below).
Nonetheless I tried to reduce it down to 30 MHz and also change all timing parameters to 15, no change whatsoever.
My FMC clock settings are:
* Use HCLK3
* sys_clk = 480 MHz
* HPRE = 2
-> HCLK3 = 240 MHz
* hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2
-> Should give 120 MHz
The thing is, the behavior in itself is completely stable, independent of the timing.
As I currently use the SDRAM only for LCD, I can work around by adding 2 to all Addresses before writing.
The bad thing is that I cannot use aligned 4-byte writes doing so.
And ... I really would like to know what's going on..
BTW, talking about SRAM, may I come with an additional question for you or another reader:
The STM32H745-DISCO has a 128MBit SRDAM with 32 bit bus mounted, however only 16 data lines are connected.
Am I correct in assuming that I can only use half of the RAM because of the missing D-lines?
I don't see any mechanism to access the other bits.
Or am I missing the obvious?
regards
Louis
2020-01-05 08:32 AM
For your information and to help people who may make the same mistake as I:
I could solve the problem.
I had an incorrectly configured CAS latency in the SDRAM's mode register.
Now that I configured the latency the same (3) on both sides, it works.
regards
Louis