[STM32H730ZBT] FMC external SDRAM loses every second byte

[sebxx4]

Continuation of this thread.

Hello, 

I've wired SDRAM (AS4C4M16SA-5TCN)  with STM32H730ZBT. Connection works, I can read/write data, but every other byte. 

Let's start with array declaration:

uint8_t *externalRAM = (uint8_t*)0xC0000000;
/* USER CODE END PV */

Then I'm trying to write some bytes to this array, ie:

externalRAM[0] = 0xAA;
externalRAM[1] = 0xAA;
externalRAM[2] = 0xAA;
externalRAM[3] = 0xAA;

  And to read it:

uint8_t test[4];
test[0] = externalRAM[0];
test[1] = externalRAM[1];
test[2] = externalRAM[2];
test[3] = externalRAM[3];

And this is the result:

Sometimes test[1] has 0xAA too, but mostly it's 0. I've tried to lower FMC frequency or change memory timings. What does this look like?

[mƎALLEm]

Could you please do the same test with 8-bit access after resoldering the NBL pins? if it's not working, could you please configure SDRAM memory space as device or strongly-ordered?

[sebxx4]

I could do this, but it's important to me to store whole 16 bits at once (it's faster than sending 2x 8 bits).
Why do you want me to check it?

Btw, how to configure SDRAM memory space as device or strongly-ordered? I don't see such option in MPU config.

And how about my question about read/write time? I've checked memory clock and it's about 91.7MHz, as expected.

[mƎALLEm]

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@sebxx4 wrote:

I could do this, but it's important to me to store whole 16 bits at once (it's faster than sending 2x 8 bits).
Why do you want me to check it?

We want to understand the root cause of the problem.

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@sebxx4 wrote:

Btw, how to configure SDRAM memory space as device or strongly-ordered? I don't see such option in MPU config.

---

You need to set it as not cacheable/not bufferable/ Sharable with TEX level set to 0:

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@sebxx4 wrote:

And how about my question about read/write time? I've checked memory clock and it's about 91.7MHz, as expected.

---

I can't answer that question. I'm not SDRAM interface expert.

[sebxx4]

Well, I would prefer to avoid desoldering the circuit again, but I uploaded the previous code and the problem does not occur, so it looks like the cause was a missing connection of one of the NBL signals.

If you can't help me with SDRAM performance, maybe do you know who can I ask?

[mƎALLEm]

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@sebxx4 wrote:

but I uploaded the previous code and the problem does not occur, so it looks like the cause was a missing connection of one of the NBL signals.

---

In that case, that's the issue what I was talking about from the beginning.

So need to close this thread by accepting this post:

And open a new one for the SDRAM timing. We need to separate issues in this community.

PS: unfortunately I don't have a contact to help you with the SDRAM timings.

[sebxx4]

Well, I think I managed the performance by enabling Dcache.