STM32H723 large ADC offset

[HMüll.4]

Hi,

I'm already aware of the application note from https://www.st.com/resource/en/application_note/an5354-getting-started-with-the-stm32h7-series-mcu-16bit-adc-stmicroelectronics.pdf but as it does not cover STM32H72*-MCUs, I have to afraid I need to ask it here.

I have configured some ADC-stuff for 16 bit data sampling in CubeMX but now get incredible large offsets, even when the ADC-pins are connected to GND directly. That offset is in range 2000..4000 and very instable, means floating about the full range (I except it not to be a noise-problem as for testign the pin is pulled to GND directly).

What I have configured in CubeMX:

VREFBUF-mode to internal voltage reference

Trimming Mode: factory trimming

Internal voltage reference scale: SCALE2 (around 1.8V as I expect input voltages in range 0..1,8V)

The ADC's are used without oversampling, asynchronous clock-mode, divided by 4. The clock to the ADC's is at 64 MHz (may be too high?)

ADC is running in independent mode, no continuous conversion and software-triggered start of conversion.

At the very beginning, prior to starting the ADCs, I call

HAL_ADCEx_Calibration_Start(&hadc1,ADC_CALIB_OFFSET_LINEARITY,ADC_SINGLE_ENDED);
HAL_ADCEx_Calibration_Start(&hadc1,ADC_CALIB_OFFSET,ADC_SINGLE_ENDED);

So...what could be missing? Anything to check to find the problems?

Thanks!

Edited by ST moderator to be inline with the community rules especially with the code sharing. In next time please use </> button to paste your code. Please read this post: How to insert source code

[Ozone]

I don't know details about the H7 specifically.

> The ADC's are used without oversampling, asynchronous clock-mode, divided by 4. The clock to the ADC's is at 64 MHz (may be too high?)

> ADC is running in independent mode, no continuous conversion and software-triggered start of conversion.

At the very beginning, prior to starting the ADCs, I call

What do you have connected to the ADC pins, and what sampling times you have configured ?
I would first try connecting them to GND, and expect around 0.

[HMüll.4]

> I would first try connecting them to GND, and expect around 0.

This is what I'm doing and where i get these way too high offset-values...

> what sampling times you have configured ?

What do you mean exactly with "sampling time"?

[Ozone]

> What do you mean exactly with "sampling time"?

Check the reference manual and your (Cube/HAL) application code.

And:
Does you MCU has dedicated AGND pins ?
You need to connect the input to the ADC pin and AGND.
On most Nucleo/Discovery boards, AGND is connected to GND.

[TDK]

The symptoms suggest the pin is not pulled to ground. What board is this, and which pins?

[HMüll.4]

So what we have:

AGND is connected with general GND

VDDA is connected with general VDD (3.3V)

VREF+ is left open due to the internal reference configuration

The analogue inputs at PB0/PB1 (both configured as analog inputs with "no pull") come with a voltage divider to come from the 0..10V input value down to 0..1,8V range (with an op-amp in order to decouple this voltage divider from any inputs internal resistance):

As you can see, it is a custom board, so no Nucleo or DK from ST.

[TDK]

> VREF+ is left open due to the internal reference configuration

Is VREF+ bypassed to GND with a 1 uF + 100 nF cap? Or just completely floating? It needs the caps to be stable.

[Ozone]

Have you grounded the ADC inputs directly (AIN0, AIN1) ?
And have you measured the opamp voltage at their outputs ?

> The analogue inputs at PB0/PB1 ... come with a voltage divider to come from the 0..10V input value down to 0..1,8V range (with an op-amp in order to decouple this voltage divider from any inputs internal resistance):

I suppose you know that in this kind of SA - ADC, the input source is supposed to charge/discharge the S&H capacitor to the respective potential in the configured sample time.
The S&H capacitor, together with the input impedance and external resistors, form a low-pass filter you need to match with your desired sampling frequency.

Although I think this is not you current problem, but an offset voltage on your opamp outputs.

[HMüll.4]

No, the problem also happens when I connect PB0/PB1 to ground directly, means when the whole voltage-divider and op-amp stuff is not involved.

[HMüll.4]

> Is VREF+ bypassed to GND with a 1 uF + 100 nF cap? Or just completely floating? It needs the caps to be stable.

It is completely floating, right because VREG+ is configured in CubeMX  to be set internally completely. So this capacitor is still needed, even when I do not make use of this input?