STM32H7 without SMPS - VCAP / LDO ?

[LCE]

Heyho,

about VCAP / LDO connection in STM32H7 series without SMPS, for example in STM32H733ZGT6 (LQFP-144), when using the internal LDO for core supply.
As far as I understand, the VCAP pins are for the connecting buffering capacitors to the internal LDO.
I have checked the Nucleo (H723) and Discovery (H735) schematics, and for each pin there's a 2u2 cap, but all pins are connected.

Questions:

1) Is it a must to connect all the VCAP pins together on the PCB?
If so, please give me some valid explanation. Electrically this is one net within the STM32, so I don't see why these should be connected externally, as long as each pin is closely connected to its dedicated external capacitor.

In a LQFP-144 package these pins are quite far apart, and I'd like to NOT connect these pins - the layout will be ugly enough.

2) Is there an upper limit on the capacitor size?
Assuming I don't bring the pins together - see 1) - I'd like to be on the safe side and give each pin a little more than the 2u2 (10u). That a problem?

I have not seen an LDO over the last 15 years which had stability problems with a little more output buffering - but who knows what's built into the H7s ? Hopefully ST does!

Thanks in advance!

[Danish1]

Stm32 microcontrollers are amazingly fast CMOS devices. Particularly the stm32H family.

The point about CMOS is power is not consumed when CMOS gates are sitting idle - they just take large gulps of current whenever they change state (high-to-low or vice versa).

The point about amazingly-fast is that the gulps are extremely quick. So quick that the inductance of even a few millimetres of pcb track has too much inductance to allow the current to flow without excessive voltage drop. Even though they are on the same net, a current-drain on one side of your chip is too far away from a capacitor on the other side of the chip. ST have done extensive testing and have found that the only way they can guarantee reliable operation over the range described in the data-sheet is with all capacitors. That's not to say your bench tests will fail if you omit a cap or it's out of spec; just that ST won't guarantee it will work reliably.

As to maximum capacitance, there might be multiple issues.

• ESR: high capacitance might imply high ESR, perhaps due to different technology (Electrolytic or tantalum versus ceramic) or different internal physical construction.
• Charging time - ST expect to be able to turn on the regulator and have its output up-to-voltage within a certain time-window. Increase the capacitance and the actual charging-time might be longer even with the regulator delivering as much current as it can.
• Stability - these regulators are not optimised for ease-of-use; they are shoe-horned into the same process as the main microcontroller's transistors are made of, operate at very low voltage and might go unstable if you go outside the recommended range.

My personal feeling is that you must use one capacitor per pin. So the layout will always be difficult.

But I suspect the use of 10uF ceramic in place of each and every 2.2uF, if that makes your bill-of-materials easier, will not be an issue.

[AScha.3 · Accepted solution]

Hi,

> 1) Is it a must to connect all the VCAP pins together on the PCB?

No. I made boards with H733, H743, H7A3 , (all ZIT 144pin) no connected vcap pins; all running fine from beginning.

> 2) Is there an upper limit on the capacitor size?

Maybe - i just used the 2u2 at each pin, dont want begin "discussion" with the internal LDO. :)

( -> for production ! )

But afaik i also tried with 10u  0805 on a board, also working. (i like these 10u cercaps.)

But i had to add 1x 470 r par. to a 10u vcap , because cpu needed to long for restart/reset , these caps holding the core "long time" at a voltage, that didnt a clean reset. With 470 r as pull down load working fine then.

Also on VDD , not using any electrolytic cap, just some 10u close to cpu and one 10u at the AZ1117cw33 LDO.

[LCE]

@Danish1 thanks! That first part of your reply from ST or ChatGTP ? ;)

@AScha.3 thanks for some real-life input! If I have the space, I'll put another 0603 footprint in parallel to the VCAP-caps.

I have not used any non-ceramic capacitors in the last 15 years or so, except for some special power circuits (alu) or a few big foil caps in some signal paths. Luckily, most of our projects are low voltage / low power stuff.

[Danish1]

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@LCE wrote:

@Danish1 thanks! That first part of your reply from ST or ChatGTP ? ;)

Er, how would I tell? (Quickly looks in the mirror). Yup that's the same ugly mug as I saw this morning.

I wrote all that myself. Maybe ST would have a better supply of adjectives. I don't know how to chatgpt.

[LCE]

@Danish1 :D
About the "quick gulps", I know about that, doing mixed signal PCBs for more than 20 years now, that's why I thought that this connection of the different VCAP pins on the PCB does not make any sense, it might rather be another source of noise. Each VCAP pin with one closely placed cap, that's for sure!

And yes, the internal LDO is probably not the best it could be, but adapted to the rest of the internal silicon and rather designed simple to just make it work within limits (as maximum load capacitance).