STM32H7 SRAM ECC Triggered unexpectedly

ChrisO · ‎2025-05-16

Hi,

I am testing the ECC on DTCM on the STM32H7A3ZI. At start of day I initialize all of DTCM apart from a single test location. I have a test which reads from that uninitialized location and successfully provokes the SRAM ECC interrupt, correctly reporting the address for the uninitialized location. (I am following application note AN5342).

However, I am finding that the same ECC error is raised in other circumstances, when I am confident that my code is not reading the test location. This happens when the IDE is not connected, so it is not the IDE which is reading that location.

I have another test that provokes flash ECC errors, and it is currently the code of this test that somehow provokes the SRAM ECC error as well as the flash ECC error. However I don't think this code is reading the uninitialized location (and I have also seen other code provoke the problem). The address reported in the FAR register is always that of my uninitialized test location.

I could imagine that the processor might read that location if cacheing or speculative read-ahead operations were happening, but I believe that no such cacheing would apply to DTCM.

Could you give any ideas about why this might be happening?

Thanks,

Chris

mƎALLEm · ‎2025-05-16

Hello @ChrisO and welcome to the ST community,

Maybe you need to explain in details what are these circumstances in this statement:

@ChrisO wrote:

However, I am finding that the same ECC error is raised in other circumstances, when I am confident that my code is not reading the test location.

I don't think flash ECC errors has a relation with RAM-ECC. Both ECCs are different. But who knows: what if you disable that flash ECC test?

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