STM32H7 RTC accuracy with 32.768 kHz LSE quartz in VDD mode and VBAT mode

[ChrSch]

Hello,

in our design with STM32H753ZIT6 I've adjusted the C0G load capacitors on the LSE 32.768 kHz crystal so that the real-time clock is now very accurate (less than 1 second error in 24 hours). I've always performed the calibration in VBAT mode at a voltage between 2.3 and 3.2 V.

However, now I've noticed that in normal VDD mode with active controller, the real-time clock is running significantly too slow, with an error of 90 seconds in 24 hours. I've ruled out the VBAT supply voltage as the cause. Any ideas what could be causing this large error in normal VDD mode?

Thank you!

[ChrSch · Accepted solution]

I did the test with the calibration signal at PC13.

Here is the signal in VBAT mode. (I turned the persistence of the scope to infinity.) The edged are very stable at the same position.

And here the signal in normal running mode, again with infinity persistence:

There is a significant jitter. If I stop the CPU with the debugger, the frequency is stable again.

I have no explanation, why the frequency is not 512 Hz.

I changed the setting for the drive strength to medium-low and to medium-high (regarding the errata). With both setting I can achieve a stable frequency (of 512 HZ! ?:-/) in battery and powered-up mode. I decided to use the real medium-high mode and I'm performing a long-term measurement now. I hope this solves my issue.

[mbarg.1]

512Hz clock is derived directly from LSE - no way debugger can change frequency - by design.

Your picture shows that debugger connections inject some noise into oscillator - it is an analog problem linked to ground loops and / or power supply bypass.

Share PCB design if you want more help.

Or, before, double check loading your sw into a Nucleo board and repeate tests - square wave is correct even with debugger operation.

There is a last remote possibility: you have direct access to RTC registers - usually you set up at boot, and forget - but sw can overwrite them and modfy count - you can chcekc setting a breakpoint any write to RTC registers or expanding a lot  square wave down edge - if there is an error in count, you will see multiple vertical lines in next  as register are triggered by LSE clock - if there is injected noise, no discrete lines.

Let know what is the case - and eventually mark as a a solution. Mike

[AScha.3]

>I changed the setting for the drive strength to medium-low and to medium-high (regarding the errata). With both setting I can achieve a stable frequency (of 512 HZ! ?:-/) in battery and powered-up mode.

So you had it at low drive strength ? That never worked for me at all in a reliable way,

so always set LSE drive high, to have lowest impact from surrounding signals. 

btw 

In my actual design i use an LSE oscillator to avoid these silly problems with the LSE crystal drive from cpu/chip.

digikey -> 2195-OM-7604-C7-32.768KHZ-20PPM-TA-QCCT-ND  , 0.3 uA typ. , 20ppm , 92 ct .