Hello,
I'm using the HAL_SPI_TransmitReceive() to communicate to a NOR flash via single SPI in polling mode using HW CS. I'm on H753 Rev.V silicon using the latest HAL library.
I checked out the SS output management in master mode (SSOM=1) but made strange observations depending on the baudrate and MIDI settings. For my test here I set MIDI=0 because I am only interested in the MSSI parameter.
I found out that if the baudrate is equal or lower than 12.5MHz, the CS signal is set active for the whole transfer, just as expected by me:
Note that the flash responds on MISO to the read command.
But if the baudrate is higher than 25MHz, the CS signal is set inactive after one or multiple data bytes:
Because the command/address/dummy byte sequence is broken by CS pulses, the flash does not respond.
It the baudrate is increased, e.g. to 100MHz, CS is set inactive between each single byte.
Regarding the RM0433, this should only happen if MIDI is greater than 0:
When SSOM=1, SP=000 and MIDI>1 the SS is pulsed inactive between data
frames, and kept inactive for a number of SPI clock periods defined by the MIDI
value decremented by one (1 to 14).
Here is the CFG2 register content before the HAL_SPI_TransmitReceive() function call:
>>> bin(0xe0400000)
'0b 1110 0000 0100 0000 0000 0000 0000 0000' 
If I disable SS output management (SSOM=0), CS is not disabled between the transfer, just as expected.
But then there is no way to specify a delay between CS active and first SCLK.
Any idea what is wrong here?
