Hello TDK,
thanks for you answer. I will come back to you once I try this out on my board. I have another question regarding the initialization step for the ADC periphery. According to the reference manual you can select between synchronous and asynchronous Clokcking (kernel_clk). I see that the ADC provides 3 multiplex possibilites which is PLL2P, PLL3R and PER_CK , although PER_CK could be HSE or HSI or CSI. Which configration mode is seen as synchronous clocking when I need to call HAL_RCCEx_PeriphCLKConfig for the ADC periphery initialization or do I need to skip this and call another function ?
I see in the RCC header files following #defines for the ADC:
/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */
#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
The code which is initialized by Cumbemx uses ADC_CLOCK_ASYNC_DVx defines which means the ADC is fed by a asynchrnous clock?
How can I change this to a synchronous PLL?
Moreover, which maximum frequency can be handled by the ADC periphery when used during operating as the multiplexed PLL can provide different frequency values?
