STM32H563 VDDA rising and falling control timig

[tomy]

I'm thinking to control for VDDA on the STM32H563.

I'm considering by the red line in the diagram below, but are there any problems?

I'm considering when VDDX independent from VDD, can be rising and falling VDDA.

Please advise for me.

Best regard.

[AScha.3]

Hi,

your plan seems ok. (just make sure, never have vdda > vdd active.)

from ds H563:

So vdda can be zero, if not using adc..etc , when vdda < 2.1V .

btw

If you want smps for vdd for low power consumption , why not using the version with internal smps (H56xxxxQ ) ?

[tomy]

Hi Chief  AScha.3.

Thank you for your advice.

I'm relieved to hear that my plan seems to be fine.

I understood as below figure when ADC using by your advice.

Is my understanding correct or wrong?

And thank you for suggesting SMPS model.

I want to use Ethernet and many GPIOs.
So, I'm selecting without SMPS.

Please advise for me.

Best regard.

[AScha.3]

Hi,

just thinking about sense or nonsense of power supply design:

i had similar conditions , 24 V general power source; i decided step down to 5V (same as you do);

(5V anyway needed for some signal drivers, RS485 etc, and compatibility to 5V circuits.)

then just (linear) 3v3 LDO for cpu , vdd+vdda+vusb ; 

if the H563 at max speed, core is at about 32mA at max. speed (250M) , + all peripheral max. 100mA;

so the LDO will have (1.7v * 100m) 0.17 W max. power dissipation , or 54mW for core alone;

with a buck for vdd and LDO for vdda and added circuitry to keep the vdd-vdda "tracking", you might reduce it by 0.12W in best case.  

Now question is : is reducing power "waste" by 0.12W worth the added circuit, two regulators and some risk (to violate the correct working conditions for cpu) really worth it ?

Because something like an TS1117-3.3 (or AMSxx) you need anyway for vdda , and they can make 1A out anyway,

so using this for all cpu supplies is cheaper, needs less space and no risk to have bad vdd-vdda relation.

btw 

I have it running at 200M, at vos1 + some peripheral i need, so it needs about 50mA; 

temperature rise is about 5° above ambient;

dual supply, LDO + smps on 3v3 , would just gain about 80mW power loss in LDO - not worth thinking about too much.

[tomy · Accepted solution]

Hi Chief  AScha.3.

Thank you for your advice.

I researched NucleoSTM32H563ZI schematic diagram.
VDDA connected VDD.

VDD generate by large linear regulator (output current 1.3A).

This is same of your advice.

I would consider one large linear regulator to supply for VDD and VDDA.

Thank you.

Best regard.