STM32G441 GPIO PB4 and PB6 pullup not working

[Nickelgrass]

Hello,

I am having a strage problem with setting up simple input pins on PB3, PB4, PB5, PB6 and PB7 with pullup on a G441 bare metal. I set the bits in the GPIOB_MODER and GPIOB_PUPDR acordingly and also read them back to make sure. They are correct. 

GPIOB->MODER &= ~(0b1111111111000000); // GPIOB 3 to 7 inputs

GPIOB->PUPDR &= ~(0b1111111111000000); // GPIOB 3 to 7 pullup

GPIOB->PUPDR |= (0b0101010101000000); // GPIOB 3 to 7 pullup

Strangly the PB4 and PB6 stay low most of the time as if they are floating. I can not figure out why that would be. Did I miss something special about them? I know PB4 is a JTAG debug pin but setting the MODER shoud set it as a normal input. If I pull the pin to 5V externally it goes high (PB6 is FT).

[Issamos · Accepted solution]

Hello @Nickelgrass 

According to the DS12960 Rev 5:

 After reset, a pull-down resistor (Rd = 5.1kΩ from UCPD peripheral) can be activated on PB6, PB4 (UCPD1_CC1, UCPD1_CC2). The pull-down on PB6 (UCPD1_CC1) is activated by high level on PA9 (UCPD1_DBCC1).The pull-down on PB4 (UCPD1_CC2) is activated by high level on PA10 (UCPD1_DBCC2). This pull-down control (dead battery support on UCPD peripheral) can be disabled by setting bit UCPD1_DBDIS=1 in the PWR_CR3 register. PB4, PB6 have UCPD_CC functionality which implements an internal pull-down resistor (5.1kΩ) which is controlled by the voltage on the UCPD_DBCC pin (PA10, PA9). A high level on the UCPD_DBCC pin activates the pull-down on the UCPD_CC pin. The pull-down effect on the CC lines can be removed by using the bit UCPD1_DBDIS =1 (USB Type-C and power delivery dead battery disable) in the PWR_CR3 register.

I think this is the reason behind this behaviour in those 2 pins.

Best regards.

II

[Nickelgrass]

Thanks very much! My problem was that I looked at rev 1 of the datasheet, that did not have that information.