STM32G431KB strange DAC slew rate behaviour

[etheory]

I assume this issue applies to DACs across all the MCUs but I am testing on a Nucleo-G431KB so I'll stick with the scientific facts.

When I write a 12bit DAC value greater than 4060, the "down" slew rate in buffered output mode drops off a cliff.

For values between 0 and 4060 the up and down slew rates are symmetrical.

M​y assumption is that the analog output buffer is adding a slew issue due to latching up near the supply rails but the docs don't seem to mention this.

Aside from limiting the DAC output range or moving to an external buffer (which for parts count reasons would be nice to avoid), has anyone else experienced this or has an insight into why it happens?

The below image has the DAC going from 0 to 4095 then 0 to 4060.

See how the "down" section is quite slow from 4095 to 0, but fast from 4060 to 0.

The blue waveform is a timing reference from a PWM on the same timer driving the DAC:

[Uwe Bonnes]

What is your VDDA and VREF? If both are the same, the buffering OP might be in saturation, where recovery takes some time. Try with e.g. VDDA = 3.3V and VREF 3.0 V to have some margin.

[K.Oku]

​Hello,

As you are using output buffer, the output voltage is limited at 0.2V to VREF+-0.2V

If output buffer is saturated, as output buffer is opamp structure, it's feedback is not correctly closed. then output voltage goes down it needs some time to be correctly biased. So if you would like to use buffered mode with correct beahvioue, please use between 0.2V to VREF+-0.2V.

Regards

Kenichi