STM32G0x ADC CFGR1 clears Resolution bits on EXTSEL bit modification

[danielbathtub]

Hi, 

When I clear the EXTSEL bits in the ADC1 CFGR1 register, my resolution bits also get cleared ?. My ADC randomly changes resolution. Below is screenshots of the code. 

Why does this happen ?, I can disable the ADC to write the RES bits to what they were. Don't really want to do that unless I have to. 

[KDJEM.1 · Accepted solution]

Hello @danielbathtub ;

When you writing any bits in the ADC_CFGR1 register of STM32G0x while the ADC is enabled (ADEN bit set), the RES[1:0] (resolution) bits are reset. This behavior is documented in STM32G0 errata sheets like as in STM32G050 errata sheet.

Thank you.

Kaouthar

[MKANO.2]

Hi danielbathtub,                                                                                                                                                           The issue is already documented in Errata sheet ES0545 - Rev 3 that when modifying the ADC_CFGR1 register while ADEN bit is set  will resets RES[1:0] bit . A workaround is proposed for that.                                                          Mariem