I read the above table as
- nominal HSI frequency is 16Mhz + 0.5% - 0.75%
- due to temperature-induced drift, this changes to 16Mhz +2% -2.75%
- voltage-induced drift is mostly negligible
To avoid error, the receiver has to correctly sample the stopbit, i.e. roughly speaking, the cumulative error from startbit to stopbit cannot be more than half the bit duration (details involve the exact sampling method and differ very slightly from this rule of the thumb). For the usual start+8+stop scheme it's roughly half bit out of 10 bits, i.e. 5%. This assumes a perfect counterpart; if your counterpart is equally imperfect, this value has to be halved. Up to now this all is baudrate-independent.
Now add the imperfection of baudrate generation; and yes, fractional baudrate is imperfect (although its exact impact is again relatively complicated to calculate exactly) and best to be considered as the worst of the two surrounding integer-divider baudrates.
Now add constant-time errors, mostly in the form of asymmetry between high and low states at the receiver, having many causes, e.g. asymmetric rise-fall time, asymmetric sampling level of receiver, jitter of PLL of the clock source (if any) etc. These of course have baudrate-dependent impact.
So, generally, HSI as USART clock source is mostly marginal. I personally would never use it in an environment where data transmission has to be ensured, i.e. it's OK for debugging on the bench, it's not OK for industrial application.
YMMV.
JW
