Stm32G030 Timer : problem by using TIM17 OC1 as internal trigger for TIM1

[DPark.7]

We use Stm32G030C8 for our project, which has only 16bit timers.

But we need 32bit timer, therefore we are going to combine two timers.

We could combine TIM1 with TIM3 successfully – TIM1 as slave and TIM3 as internal trigger (ITR2).

Unfortunately we need TIM3 for other purposes, so are going to use TIM17 OC1 as internal trigger as shown in documentation RM0454 below.

But it doesn’t work. Please check our setting for each timers and give us advice to solve this problem.

RM0454 Rev5 : Page 402

Table 69. TIM1 internal trigger connection

Slave TIM : TIM1

ITR0 (TS = 00000) : TIM15

ITR1 (TS = 00001) : Not connected

ITR2 (TS = 00010) : TIM3

ITR3 (TS = 00011) : TIM17 OC1

(We have a 64 MHz internal clock.

Prescaler for TIM17 is set with 63, because TIM17 should tick every 1 micro second. )

For TIM1 we have following setting :

 LL_TIM_InitTypeDef TIM_InitStruct = {0};

 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);

 TIM_InitStruct.Prescaler = 0;

 TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;

 TIM_InitStruct.Autoreload = 65535;

 TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;

 TIM_InitStruct.RepetitionCounter = 0;

 LL_TIM_Init(TIM1, &TIM_InitStruct);

 LL_TIM_DisableARRPreload(TIM1);

 LL_TIM_SetTriggerInput(TIM1, LL_TIM_TS_ITR3);

 LL_TIM_SetClockSource(TIM1, LL_TIM_CLOCKSOURCE_EXT_MODE1);

 LL_TIM_DisableIT_TRIG(TIM1);

 LL_TIM_DisableDMAReq_TRIG(TIM1);

 LL_TIM_SetTriggerOutput(TIM1, LL_TIM_TRGO_RESET);

 LL_TIM_SetTriggerOutput2(TIM1, LL_TIM_TRGO2_RESET);

 LL_TIM_DisableMasterSlaveMode(TIM1);

 LL_TIM_EnableCounter(TIM1);

 For TIM17 OC1 we have following setting :

 LL_TIM_InitTypeDef TIM_InitStruct = {0};

 LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};

 LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct = {0};

 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17);

 TIM_InitStruct.Prescaler = 63;

 TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;

 TIM_InitStruct.Autoreload = 65535;

 TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;

 TIM_InitStruct.RepetitionCounter = 0;

 LL_TIM_Init(TIM17, &TIM_InitStruct);

 LL_TIM_DisableARRPreload(TIM17);

 TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_TOGGLE;

 TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;

 TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;

 TIM_OC_InitStruct.CompareValue = 0;

 TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;

 TIM_OC_InitStruct.OCNPolarity = LL_TIM_OCPOLARITY_HIGH;

 TIM_OC_InitStruct.OCIdleState = LL_TIM_OCIDLESTATE_LOW;

 TIM_OC_InitStruct.OCNIdleState = LL_TIM_OCIDLESTATE_LOW;

 LL_TIM_OC_Init(TIM17, LL_TIM_CHANNEL_CH1, &TIM_OC_InitStruct);

 LL_TIM_OC_EnableFast(TIM17, LL_TIM_CHANNEL_CH1);

 TIM_BDTRInitStruct.OSSRState = LL_TIM_OSSR_DISABLE;

 TIM_BDTRInitStruct.OSSIState = LL_TIM_OSSI_DISABLE;

 TIM_BDTRInitStruct.LockLevel = LL_TIM_LOCKLEVEL_OFF;

 TIM_BDTRInitStruct.DeadTime = 0;

 TIM_BDTRInitStruct.BreakState = LL_TIM_BREAK_DISABLE;

 TIM_BDTRInitStruct.BreakPolarity = LL_TIM_BREAK_POLARITY_HIGH;

 TIM_BDTRInitStruct.BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;

 TIM_BDTRInitStruct.AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;

 LL_TIM_BDTR_Init(TIM17, &TIM_BDTRInitStruct);

 LL_TIM_SetTriggerOutput(TIM17, LL_TIM_TRGO_UPDATE); // LL_TIM_TRGO_OC1REF doesn’t work either

 LL_TIM_EnableCounter(TIM17);

[waclawek.jan · Accepted solution]

Read out and check/post both timers' registers.

Note, that you need to enable TIM17_CH1 in TIM17_CCER, and also have TIMx_BDTR.MOE set, as if you would output PWM onto a pin - except that you don't set any pin for TIM17_CH1 in GPIO.

JW

[DPark.7]

Great! Thanks a lot for waclawek.jan!

The key points by TIM17 were :

 LL_TIM_OC_EnablePreload(TIM17, LL_TIM_CHANNEL_CH1);

 TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_PWM1;

 TIM_BDTRInitStruct.AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_ENABLE;

Here the setting for TIM17, that works :

 LL_TIM_InitTypeDef TIM_InitStruct = {0};

 LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};

 LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct = {0};

 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17);

 TIM_InitStruct.Prescaler = 63;

 TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;

 TIM_InitStruct.Autoreload = 65535;

 TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;

 TIM_InitStruct.RepetitionCounter = 0;

 LL_TIM_Init(TIM17, &TIM_InitStruct);

 LL_TIM_DisableARRPreload(TIM17);

 LL_TIM_OC_EnablePreload(TIM17, LL_TIM_CHANNEL_CH1);

 TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_PWM1;

 TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;

 TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;

 TIM_OC_InitStruct.CompareValue = 10;

 TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;

 TIM_OC_InitStruct.OCNPolarity = LL_TIM_OCPOLARITY_HIGH;

 TIM_OC_InitStruct.OCIdleState = LL_TIM_OCIDLESTATE_LOW;

 TIM_OC_InitStruct.OCNIdleState = LL_TIM_OCIDLESTATE_LOW;

 LL_TIM_OC_Init(TIM17, LL_TIM_CHANNEL_CH1, &TIM_OC_InitStruct);

 LL_TIM_OC_DisableFast(TIM17, LL_TIM_CHANNEL_CH1);

 TIM_BDTRInitStruct.OSSRState = LL_TIM_OSSR_DISABLE;

 TIM_BDTRInitStruct.OSSIState = LL_TIM_OSSI_DISABLE;

 TIM_BDTRInitStruct.LockLevel = LL_TIM_LOCKLEVEL_OFF;

 TIM_BDTRInitStruct.DeadTime = 0;

 TIM_BDTRInitStruct.BreakState = LL_TIM_BREAK_DISABLE;

 TIM_BDTRInitStruct.BreakPolarity = LL_TIM_BREAK_POLARITY_HIGH;

 TIM_BDTRInitStruct.BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;

 TIM_BDTRInitStruct.AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_ENABLE;

 LL_TIM_BDTR_Init(TIM17, &TIM_BDTRInitStruct);

 LL_TIM_CC_EnableChannel(TIM17, LL_TIM_CHANNEL_CH1);

 LL_TIM_EnableCounter(TIM17);