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STM32G030 RTC LSE clock instability

NiTr0man
Visitor

I tried to use internal RTC with LSE clocking in device which has GSM/GPRS module (GSM part decoupled from MCU part by ferrite beads in power lines and resistors in data lines). In first PCB revision (no separate ground region under crystal) I noticed significant RTC slowdown at GPRS transactions (0.2-0.4 seconds at each GPRS data transaction, when I soldered wires to GSM part ground and VCC pads - clock slowdown is increased). I've fixed board layout according to design recommendations (separate ground regions, ground traces around quarts lines, extra ferrite bead in CPU power line) but it doesn't affect clock instability at all.

Vcc is decoupled to ground after ferrite bead by 22pF and 100nF capacitors, before ferrite bead there's a 100uF tantalum capacitor after LDO. Vbat is decoupled by 100nF capacitor and 2x22pF capacitors (there are places for different external RTC modules). Quartz is one with 12.5pF load, load capacitors are 22pF each (I experimented with smaller values - nothing was changed). Driving strength is set to high. PC13 is set as output, low level.

Here's piece of board with quartz, power and Vbat lines. X10 is place for ground shield (shielding doesn't change anything on earlier board prototype).

NiTr0man_0-1754295334425.png

What's wrong with it? Is there any option to make it stable in high-EMI environment? when I've tested older board revision, there was clock slowdown even when device's GSM module was switched off but there was a second such device with GSM placed in 10-20cm near it.

External RTC MEMS module will be a good solution, but I expected to use internal one...

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