STM32F746 Disco clear memory section

[MFawzy]

I Have STM32F746 Disco and i have a memory section that sould be initialized to zero.

and the aim behind this is to keep the memory content whenever the board is rest.

but unfortanlty, this section is being clear every time i restart the debuger.

the section is holding structure which is defined as the following:

PROBE_strExceptionInfoType objstrExceptionInfo __attribute__ ((section (".ramException")));

i tried the same criteria with STM32F3 and STM32F4 and it worked but it didn't work with STM32F7

the linker is attached.

Any idea?

Best Regards,

[Tesla DeLorean]

You want it zero'd or you want it left uninitialized so it survives reset. Your question is poorly stated.

Code in startup.s is responsible for memory initialization and clearing.

If using the linker script make sections NOLOAD

Or use pointers, and don't tell the linker about the memory you don't want it touching.

  .ramException (NOLOAD) :
  {
    . = ALIGN(4);
  } > CRASH_DUMP_PART

[MFawzy]

Thank you, this fixed the issue of the clearing for the memory. but i'm getting strange phenomna that is shown with STM32H7 and SM32F7 that the memory isn't cleared when i rest the debuger but the existance data is being distorted. Any Idea?

[Tesla DeLorean]

The MCU doesn't clear the memory,​ it will have undefined content in the memory cells when it first starts and may retain content whilst still powered, directly or parasitically.

[Tesla DeLorean]

If you're using it to stash content perhaps add some kind of checksum or signature which you subsequently invalidate once used.

Perhaps look at RTC/ BKPRAM and tamper type methods for clearing. ​

[MFawzy]

I'm using a guide to mark the content, so i know when the data being garage, the issue that I was expecting as long as the target didn’t lose the power so the memory content shall be the same even with multiple reset to the microcontroller as long as the memory isn’t cleared by the controller itself.

But I’m looking for technical clarification, why the memory is being corrupted?

please note that it sounds that it a phenomna with M7 while it isn't with M3 and M4

[Tesla DeLorean]

Well the M7 with caching you have to ensure the writes you perform find their way all the way into the memory. The flush is DCache Clean, and __DSB() for basic memory fencing of the Write Buffers

[Tesla DeLorean]

BKPSRAM at 0x40024000,shouldn't be cached.

DTCMRAM not either

[MFawzy]

How can the Dcashe being flush? Is it some kind of instructions?

[Piranha]

For this purpose just move that structure to the beginning of DTCM. But generally one cannot develop code for Cortex-M7 without understanding cache maintenance and memory barriers.