2017-10-14 08:55 AM
Hi,
i generated with CubeMX some code.
I want that timer 2 is triggering timer 3.
If an overflow on Timer 2 occurs Timer 3 should count up 1.
I tried some configurations but nothing worked - no interrupt on timer3
When i set the output trigger (timer 2) to the same Channel as input trigger (timer 3) it isnt working.
This is my configuration code:
TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM2 init function */ void MX_TIM2_Init(void) { TIM_ClockConfigTypeDef sClockSourceConfig; TIM_MasterConfigTypeDef sMasterConfig; htim2.Instance = TIM2; htim2.Init.Prescaler = 54; htim2.Init.CounterMode = TIM_COUNTERMODE_UP; htim2.Init.Period = 250; htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4; htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim2) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); } } /* TIM3 init function */ void MX_TIM3_Init(void) { TIM_SlaveConfigTypeDef sSlaveConfig; TIM_MasterConfigTypeDef sMasterConfig; htim3.Instance = TIM3; htim3.Init.Prescaler = 1; htim3.Init.CounterMode = TIM_COUNTERMODE_UP; htim3.Init.Period = 8000; htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim3) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); } sSlaveConfig.SlaveMode = TIM_SLAVEMODE_EXTERNAL1; sSlaveConfig.InputTrigger = TIM_TS_ITR0; if (HAL_TIM_SlaveConfigSynchronization(&htim3, &sSlaveConfig) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); } }
2017-11-15 07:32 AM
Hello
fabian.borstel
,The example titled 'TIM_CascadeSynchro' shows how to synchronize TIM2 and Timers (TIM3 and TIM4) in cascade mode.
You may take this example as a reference to correctly configure your peripheral.*sSlaveConfig.SlaveMode = TIM_SLAVEMODE_GATED;
*sSlaveConfig.InputTrigger = TIM_TS_ITR1; You may refer to table 'TIMx internal trigger connection' for more details on ITRx connections for each Timer.Khouloud.
2017-11-15 08:14 AM
Maybe you would want to understand what's going on instead of just clicking; refer to the timer chapters of your RM, mainly the timer registers subchapter.
If an overflow on Timer 2 occurs Timer 3 should count up 1.
First, on Timer2, set TRGO (trigger out) to update event: TIM2_CR2.MMS = 0b010.
Then, on Timer3, set the TRGI (trigger in) source to the trigger output from TIM2, look it up in TIMx internal trigger connection table. I use 'F407, for me for Slave=TIM3 and TIM2_TRGO it's ITR1, i.e. TIM3_SMCR.TS=0b001.
Then you want to use this signal - which is input to the 'slave mode controller' of the timer, as clock input, instead of the internal (APB) clock; thus you set TIM3_SMCR.SMS=0b111.
This is all for the 'interconnection'. With setting up both TIM2 and TIM3 to run (i.e. as a bare minimum setting ARR to nonzero and enabling counter by TIMx_CR1.CEN=1) you should see TIM3 running at the rate of TIM2's overflow.
Try in debugger, you don't need to write any code and it's fun. Don't forget to enable clocks in RCC first.
Now translate this to Cube parlance if you want. I don't Cube.
JW
2018-03-30 11:06 AM
Dear Fabian
I produced a tutorial explaining how to chain two timers
https://community.st.com/0D50X00009bMM8gSAG
I would appreciate your feedback and possible improvments
Bye
JC
2018-03-30 11:43 AM
'
I want that timer 2 is triggering timer 3. '
read the datasheet about how to chain two timers.
you may get there faster that way than through the messy city of CubeMX.