Posted on November 11, 2015 at 19:32
here is the code when I call a read:
Hi,
I am working on a custom board with the STM32F746IGT6. in witch is a FTDI Parallel-USB converter is connected to the FMC. My problem is that when I try to read data to ''fast'' from the FMC(after a while, and only sometimes) the FMC reads twice for one cycle. And the read function returns the result from the last transfer. This error is only sometimes and I didn't find any relationship with the content of the data. If I slow the velocity in them I pull data (> 2ms) then I have no more errors. The following image showsthesporadically
two reads at the same call. The yellow line is the read trigger. The blue line is the write trigger. Andthe green lineis an output pin that I trigger with software to recognizewhentheread function is called.
here is the code when I call a read:
static inline u8 FTDI_RX(void){
return (*(__IO u8*) (NOR_MEMORY_ADRESS3 + FSMC_ADD_FTDI)); // (uint32_t)0x68000000 + 8
}
char FTDI_READ(void){
char tmp = 0;
if (FTDI_canRead()) { //READPIN(C, 14)
SETPIN(H, 14); //Green singal on
tmp = FTDI_RX();
RESETPIN(H, 14); //Green singal off
FTDI_mode = 1;
return tmp;
} else {
return 0;
}
}
NOR_HandleTypeDef hnor1;
FMC_NORSRAM_TimingTypeDef Timing;
hnor1.Instance = FMC_Bank1;
hnor1.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
//Duration of the address setup phase
Timing.AddressSetupTime = 7; //0-15 4
//Duration of the address hold phase
Timing.AddressHoldTime = 7; //1-15 3
//Duration of the data setup phase
Timing.DataSetupTime = 20; //1-255 5
//Duration of the bus turnaround phase
Timing.BusTurnAroundDuration = 5; //0-15 1
//Number of AHB clock cycles (HCLK) to build one memory clock cycle (CLK)
Timing.CLKDivision = 3; //2-16 2
//Number of clock cycles to issue to the memory before the first data of the burst
Timing.DataLatency = 3; //2-17 2
Timing.AccessMode = FMC_ACCESS_MODE_A;
/*
- Data/Address MUX = Disable
- Memory Type = SRAM
- Data Width = 16bit
- Write Operation = Enable
- Extended Mode = Enable
- Asynchronous Wait = Disable
*/
hnor1.Init.NSBank = FMC_NORSRAM_BANK3;
hnor1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
hnor1.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
hnor1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
hnor1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
hnor1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
hnor1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
hnor1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
hnor1.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
hnor1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
hnor1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
hnor1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
hnor1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
hnor1.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE; //
hnor1.Init.PageSize = FMC_PAGE_SIZE_NONE;
// Initialize NOR control Interface
FMC_NORSRAM_Init(hnor1.Instance, &(hnor1.Init));
// Initialize NOR timing Interface
FMC_NORSRAM_Timing_Init(hnor1.Instance, &Timing, hnor1.Init.NSBank);
// Initialize NOR extended mode timing Interface
//FMC_NORSRAM_Extended_Timing_Init(hnor1.Instance, NULL, hnor1.Init.NSBank, hnor1.Init.ExtendedMode);
// Enable the NORSRAM device
(hnor1.Instance)->BTCR[(hnor1.Init.NSBank)] |= FMC_BCR1_MBKEN;STM32F74xxx STM32F75xxx Errata sheet
''2.5 FMC peripheral limitation
2.5.1 Dummy read cycles inserted when reading synchronous memories
Description
When performing a burst read access to a synchronous memory, two dummy read accesses are performed at the end of the burst cycle whatever the type of AHB burst access. However, the extra data values which are read are not used by the FMC and there is no functional failure.
Workaround
None. ''
Does some one have an Idea what I am doing wrong? I apologize for my rusty English. Best regards. Robert #stm32f7-fmc
Posted on November 12, 2015 at 17:10
The yellow signal represents the read function of the FMC at the pin NOE
The green signal represents the time used by the FMC access
The blue signal represents the time used by the interrupt.
The assembler code of my test function is:
Hi Jan,
Thank you for your post. It helped me to locate the problem. In fact the problem is an interrupt intermediately or perhaps between the FMC access. It creates a second read from the same address after the interrupt is ended. To test this I used the following code running in the main function:
1.
SETPIN(H, 14); //green signal high
2.
tmp = (*(__IO uint8_t*) (NOR_MEMORY_ADRESS3)); //yellow signal.
3.
RESETPIN(H, 14); //green signal high
SETPIN(H, 14);
8001be0: 4b15 ldr r3, [pc, #84] ; (8001c38 <
FTDI_Read
+0x78>)
8001be2: f44f 4280 mov.w r2, #16384 ; 0x4000
8001be6: 619a str r2, [r3, #24]
tmp = FTDI_RX();
8001be8: 4b14 ldr r3, [pc, #80] ; (8001c3c <
FTDI_Read
+0x7c>)
8001bea: 781b ldrb r3, [r3, #0]
8001bec: 73fb strb r3, [r7, #15]
RESETPIN(H, 14);
8001bee: 4b12 ldr r3, [pc, #72] ; (8001c38 <
FTDI_Read
+0x78>)
8001bf0: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
8001bf4: 619a str r2, [r3, #24]
1.
__disable_irq();
2.
tmp = (*(__IO uint8_t*) (NOR_MEMORY_ADRESS3));
3.
__enable_irq();