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T
taeun
Associate II
May 26, 2025
Solved

question about stm32h750bdk ExtMem_boot

  • May 26, 2025
  • 2 replies
  • 653 views

 

Inside the QSPI_EnableMemoryMappedMode function, the dummy cycles are MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR - 1.
MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR is defined as 6U.
The datasheet for MT25TL01G states that the DTR QUAD INPUT/OUTPUT FAST READ value is 8. 
Why is MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR defined as 6?

 

Best answer by KDJEM.1

Hello @taeun;

 

The dummy cycles "s_command.DummyCycles = MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR - 1;" depend on the QSPI clock frequency and on parts specification as mentioned in the memory datasheet.

KDJEM1_0-1748263581294.png

In the ExtMem_boot case QSPI clock is 50 MHz, that why dummy cycles are 5.

KDJEM1_1-1748263726828.png

For MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR as 6U definition is contradictory with the memory datasheet, I reported internally.  

Internal ticket number: 210785 (This is an internal tracking number and is not accessible or usable by customers)

Thank you.

Kaouthar

2 replies

KDJEM.1
KDJEM.1Best answer
ST Technical Moderator
May 26, 2025

Hello @taeun;

 

The dummy cycles "s_command.DummyCycles = MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR - 1;" depend on the QSPI clock frequency and on parts specification as mentioned in the memory datasheet.

KDJEM1_0-1748263581294.png

In the ExtMem_boot case QSPI clock is 50 MHz, that why dummy cycles are 5.

KDJEM1_1-1748263726828.png

For MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR as 6U definition is contradictory with the memory datasheet, I reported internally.  

Internal ticket number: 210785 (This is an internal tracking number and is not accessible or usable by customers)

Thank you.

Kaouthar

To give better visibility on the answered topics, please click on "Best answer" on the reply which solved your issue or answered your question.
T
taeunAuthor
Associate II
May 27, 2025

one more question.

Then why is it 2Cylce when sending MT25TL01G_READ_STATUS_REG_CMD command?

 

KDJEM.1
KDJEM.1
ST Technical Moderator
May 27, 2025

Hello @taeun;

 

It is mentioned in RM0433 that "In order to assure enough “turn-around” time for changing data signals from output mode to input mode, there must be at least one dummy cycle when using dual or quad mode to receive data from the flash memory."  

The status register data size is one byte. This mean that in quad mode we need 2 clock cycles to sample register value. 

 

Thank you.

Kaouthar

To give better visibility on the answered topics, please click on "Best answer" on the reply which solved your issue or answered your question.
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