STM32F7 debugging (stepping) impossible, IDE jumps into interrupts

[mattstein]

Posted on June 21, 2016 at 20:44

Hi there,

I want to port my graphics application from the F4 discovery to the F7 (see setup below).However I discovered that debugging is impossible because every time I want to step over a line of code, occuring interrupts are handled first. With the F4 they were handled in the background and the eclipse did not jump into the IRQHandler. On the F7 it directly jumps into the IRQHandler and step-out won't help. This is really inconvenient for a serious development. I also got this problem with my original toolchain (simple eclipse cdt with arm gnu plugin). The systick interrupt does not interfere with debugging the ''main''. Why is that?What is the difference to the STM32F4? Does the GDB need to handle the breakpoints differently? Is the STM32F7 hardware (Cortex, NVIC, IRQ priorities) different regarding debugging? I don't know where to start?Thanks for any help!!Best regards,MatthiasMy setup:STM32F7 discovery kit

Ac6 System Workbench for STM32

STM32Cube_FW_F7_V1.3.0\Projects\STM32746G-Discovery\Applications\STemWin\STemWin_HelloWorld #debugging #problem #stm32f7

[troy1818]

Posted on June 23, 2016 at 14:28

I have the same problem. It is very annoying...

I guess it should be possible to set a register somewhere to temporarily disable interrupts, but I have not found it yet.Im using plain GDB.

[js23]

Posted on June 23, 2016 at 18:05

Hi!

I personally would use some stronger word than ''annoying'' for this... I just searched the web for this topic some days ago. According to a post in the keil forum it is a ''feature'' of the r0p1 M7 core. The newer r0p2 behaves correct. (Are there any STM32F7s with the newer core?) Regards, Johannes

[mattstein]

Posted on June 23, 2016 at 20:32

Thanks for the hint! When googling Cortex M7 instead of STM32F7 I get the results. Here is the keil info: http://www.keil.com/support/docs/3778.htm

I will investigate if there are STM32F7 with newer revisions.

[Tesla DeLorean]

Posted on June 23, 2016 at 20:50

A conversation very similar to this was had the other month wrt STM32F767, with the 2MB FLASH, and 16KB caches, and FPU-D

The conclusion then seemed to be that ST had only licensed ther0p1 core. I'll review what's in the A stepping of the STM32F767ZIT6U from the late May delivery. .... From the F7..

STM32 1024 KB FLASH, 320 KB RAM, 002B003A-32345109-37343138 UNIQUE
CPUID 410FC271 DEVID 449
Cortex M7 r0p1
C0000000 FFFFFFF8 00000000
10110021 11000011 00000040
FPU-S Single-precision only

From the F7..

STM32 2048 KB FLASH, 512 KB RAM, 001B002A-33355109-36343130 UNIQUE
CPUID 411FC270 DEVID 451
Cortex M7 r1p0
C0000000 FFFFFFF8 00000000
10110221 12000011 00000040
FPU-D Single-precision and Double-precision

[nafikovr]

Posted on June 28, 2016 at 14:59

addition of these lines in initialization has helped me

  (DBGMCU)->APB1FZ = 0x7E01BFF;  (DBGMCU)->APB2FZ = 0x70003;