STM32F7, ART vs ICACHE?

[Pavel A.]

I'm starting with STM32F767 and cannot understand the thing about connection of the ITCM to ART. What is recommended: enable ART and flash access over TCM, or just enable ICACHE like in H7, and access code over AXIM?

When flash is accessed via TCM, does it remap from 0x08000000 to 0x00200000 ? (hinted by description of option bytes for boot address)

[mƎALLEm · Accepted solution]

Hello,

I suggest to refer to the AN4667 / especially the section 1.5.1 Embedded Flash memory.

So, for performance purpose:

• If the core does the access through the TCM, you have to enable the ART.
• If the core does the access through the AXI, you have to enable the CACHE.

No remap is done. Is up to the user to select from which region to boot and care about which accelerator to activate (ART or Cache).