STM32F446 SPDIFRX to I2S out possible?

[torgeirs]

Posted on December 23, 2015 at 17:38

Do anybody know if STM32F446 SPDIFRX in to I2S out is possible?

The worry is that input samplerate drifts and I2S output samplerate can't be changed without audible artifacts.I know that the clock PLL N and M has following restriction 

 '

These bits can

be written only when PLL is disabled

.'

So can the PLL be disabled, changed and enabled between two samples?I have made a program that calculates possible I2S frequencies.This is around 48kHz SF, MCLK on, samplelength 32.It looks like about 200ppm drift correction is possible. Max buffer growth about 10 samples/sec ?

https://goo.gl/photos/6LrdbyDQMdNLXwR6A

[torgeirs]

Posted on January 03, 2016 at 18:59

From 6.2.3 PLL configuration :

Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as PLL clock source, and configuration of division factors M, N, P, R and Q). So it looks like long stabelizing time must be expected. Or is the time much faster when the frequency is changed slighly? (Or 'start from beginning')To me it seems odd the samplerate can't be changed without making silence, a pop or a click.Is it really the case?(Sidenote. The first post had an error, not deviding by PLL/R. The new link shows the result with corrected code. [The text gets unreadable with picturesize under 100k, hence the link instead])

[Tesla DeLorean]

Posted on December 23, 2015 at 17:47

So can the PLL be disabled, changed and enabled between two samples?

That's highly doubtful. You'd probably want to insert/remove a sample to slew once sufficient bias accumulates. Or tune the clock source.

[torgeirs]

Posted on December 25, 2015 at 20:35

From the datasheet 3.27: 'The SPDIF-RX also offers a signal named spdifrx_frame_sync, which toggles at the S/PDIF sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms. '

A pity if the output clock can't be changed accordingly on the fly.From 3.29: 'The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.'But maybe it is the tLOCK PLLI2S lock time that makes the trouble?VCO freq = 100 MHz: 75 - 200µsVCO freq = 432 MHz: 100 - 300µsThere are 1000 available clockcycles between samples so the change in registers can't take that long?Regards Torgeir

[re.wolff9]

Posted on December 26, 2015 at 15:46

You can change the registers, but a PLL has to ''resync'' and that can easily take miliseconds. (on the other hand, if you change it only slightly, chances are it will lock quickly. But if you disable, change, reenable, you might have to start from the beginning. And doing it that way is what the datasheet mandates!). 

[Nesrine M_O]

Posted on January 07, 2016 at 11:47

Hi torgeirs,

So can the PLL be disabled, changed and enabled between two samples?Disabling and reconfiguring PLL between two samples is insecure, according to datasheet the PLL lock time ~200µs.So you can configure two PLLs: PLLR and the PLLI2S to generate different clocks and then switch between them .-Syrine-

[torgeirs]

Posted on January 10, 2016 at 14:44So that is the solution! Thank you for the answer to the riddle:-)