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STM32F437 External Memory Interface

Posted on April 13, 2015 at 14:00

In one of our embedded systems we use a MR256A08B MRAM in conjunction with a 



Sometimes (increasing with temperature) we are observing the problem that we cannot write to discrete bits of the MRAM.

We assume a timing issue.

The datasheet of the MRAM specifies a write recovery time tWHAX (address hold time after write high) of at least 12 ns.

The controller gives us only 6 ns (tHCLK + 0.5 ns), with the current timing settings.

Is there a chance to extend the 6 ns without cutting the HCLK-frequency from 180 MHz down to maybe 80 MHz?

Could the BusTurnAround parameter do this job? Unfortunately the datasheet does not clearly show what is happening during the bus turn around time.
Associate III

We have the same question using STM32F779!


Pavel A.
Evangelist III

@jerry_sandc Failures related to temperature? At which temperatures and HCLK does it fail? Well known board or something custom?


Associate III

Were making custom board, with MRAM connected to STM32F7 via FMC bus.  We plan to run at 216MHz, approximately 5nS per clock cycle.  SO.. the 'built in' delay of 1 clock after deassertion of write signal will not be enough time for our MRAM part that requires Address bus to be maintained for minimum 12 nS.   We don't know if adding to the bus holdoff will help, since the manual only discusses deassert/assertion of NE (enable signal).

We don't want to have to design board with address bus buffer for the MRAM part, but it might come down to that if we're not able to figure out FMC settings that will make this work.  

I'm reasonably confident that the external bus doesn't run at 216 MHz. For SDRAM it typically runs at 1/2 or 1/3 rate. The pins aren't rated over 100 MHz at I recall.

Are you testing this with a NUCLEO, or some other proxy?

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Associate III

hi @Tesla DeLorean the STM32F7 manual says FMC runs off of HCLK (high-speed clock, same as core)

If you can point me to something otherwise (please point to manual number, section, paragraph), please do, it might be great relief!

Anyway, thinking about this issue more over this weekend, either we build board as is, and experiment with HOLDOFF setting (time between accesses) or worst case add address latch buffer to MRAM.  


the 1 cycle write hold is fixed. This is an "annoying" (read: showstopper in some cases) feature of FSMC/FMC across all families, except, AFAIK, the newest 'U5.

@Tesla DeLorean,

100MHz means that you can make transitions at the rate of 200MHz (i.e. 5ns pulses), so that's roughly OK from that standpoint. The SDRAM portion of FMC is a very different animal from the "static" portion.