Posted on November 10, 2016 at 05:14I'm attempting to write an interrupt based driver for I2C using just the CMIS header and my wits. My understanding is that there is a data register and a shift register. For transmission SR1.TXE means the data register is empty and SR1.BTF means that both the data register and the shift register are empty.
I can handle the event when SR1.SB is set and the address + R/_W is written to the data register.
Next I get TXE and ADDR set. At this point I feel that I can assume that both the DR and shift register are empty.
If I only have a single byte to write, I write it to DR then set CR1.STOP. My assumption is that this byte is immediately transferred to the shift register and I'm setting STOP at the correct time.
If I have two bytes then I can write both but wait until the next interrupt with TXE set before setting STOP. At this point I'm assuming the shift register has been drained and the contents of the data register have transferred to the shift register and this is the correct time to do this.
Then I wait for BTF and TXE and poll for the bus to be freed but it endlessly loops here.
I feel that I have a good command of the rest of the processor/core: interrupts, GPIO, timers, SPI with DMA, UART with DMA etc but I2C is humbling me.
Thanks,
Kenny
#i2c-stm32f4
