I am working with STM32F411/13 controllers from ST. And i observe an issue with SPI reads if i-cache is enabled. More details as below:
- I do have the FLASH PRE-FETCH enable set. And Flash wait states properly configured based on the System clock.
- And as soon as i enable i-cache i observe an issue with SPI reads. Where, RXNE flag for the last byte to be read is never set. Resulting in SPI read getting blocked indefinitely waiting for RXNE to be true.
- And this issue is not seen all the time, but occurs sporadically. Which makes it even more difficult to understand the cause.
Is there is any specific sequence to follow when it comes to enabling i-cache on these parts?
Or is there any errata on this already for the said parts?
Please do share your inputs, i have been blocked due to this issue for some time already. Your inputs are highly appreciated.
