STM32F407VG Clock presclalers

[markotikvic]

Posted on August 21, 2015 at 21:02

Hello,

I have couple of questions and doubts about STM32F407VG MCU setup I would like to clarify a bit.Q1: Do all the timers have the same clock source (system clock - PLL, HSI or HSE)? Because I have to divide APB1 and APB2 timers by 4 to get them to work on a same frequency as timers 6 and 7.  It's as if only timers 6 and 7 are affected by AHB prescaler.Q2: Is there a known issues with PLL prescalers regarding the P divider? I have to set PLL_P bits to 0 and 1 (again division by 4) to get it to divide by 2 (not 4 as it should), because setting it to [0, 0] does nothing.I believe the prescaling is off because I can get data over usart 2 with no problem, meaning I am calculating the BRR values correctly, meaning I am getting the frequency right, meaning some of the prescaling doesn't work as the reference manual says.I would like some help about this, because I'm not sure anymore if I'm missing something obvious or if there really are problems.Thank you,Marko.P.S.I don't know if I should post code here, so here are links to my git repos.PLL setup:https://github.com/markotikvic/malgo-winhost/tree/master/src/clk.cUart setup:https://github.com/markotikvic/malgo-winhost/tree/master/src/uart.cMain:https://github.com/markotikvic/malgo-winhost/tree/master/src/main.c

[Tesla DeLorean]

Posted on August 21, 2015 at 22:35

There is a Clock Tree diagram in the Reference Manual, I'd strongly recommend reviewing it.

The TIM CLK source depends on which APB the timer peripheral is on (review diagrams and defines), and the divider. The TIMCLK usually comes off the APB divider one stage earlier, so is usually 2x the APB CLK except for the DIV1 cases.The APB2 TIMCLK is usually 168 MHz (AHB DIV2 *2), APB1 TIMCLK is usually 84 MHz (AHB DIV4 *2)The PLLP options a DIV2, DIV4, DIV6, DIV8, the VCO does not have a 50/50 duty, so it always needs a divide by 2The PLL should run between 192-432 MHz (PLLN), the PLL comparison frequency (PLLM) needs to be 1-2 MHz

[markotikvic]

Posted on August 29, 2015 at 23:47

Sorry for the late reply.

Thank you for your response, but unfortunately it does not help me. I am familiar with the clock tree and that is why asked the question. It seems that this only happens when I use HSE clock as PLL source. I have no problems when using HSI to clock PLL.

[Tesla DeLorean]

Posted on August 30, 2015 at 01:18

The clocks for the processor and peripherals are all derived from the same singular source PLL, HSE, or HSI. There are hard relationships between them, like teeth on a mechanical gear. The TIMCLK and APB clocks have a direct 1X or 2X relationship.

You can output internal clocks via the MCO (PA8) pin.The PLL and it's VCO have some very specific limits and constraints. It will malfunction if you get the settings wrong. The 1-2 MHz comparison frequency is important.Thing can go awry in software if the define for HSE_VALUE doesn't relate to the external clock source. ie if you've got it set for 25 MHz and your using an STM32F4-DISCO with an 8 MHz source.You can view what the system thinks it's clock are using  RCC_GetClocksFreq(&RCC_Clocks); which decomposes the RCC/PLL settings, and generates values for the AHB/APB1/APB2 clocks.

[waclawek.jan]

Posted on August 31, 2015 at 22:37

https://github.com/markotikvic/malgo-winhost/blob/master/src/clk.c:

> RCC->PLLCFGR |= (1 << 22);    /* HSE as PLL clock source entry */ > > /* Set peripheral clock multipliers and dividers. */ > RCC->PLLCFGR = ((M << PLLM_FLAG_RW) | (N << PLLN_FLAG_RW) | (P << PLLP_FLAG_RW) | (Q << PLLQ_FLAG_RW)); The second line clears the bit set in the first line. JW