STM32F407I power up problem

[shlomo]

Posted on August 02, 2015 at 15:12

Hi,

I'm using the stm32f407i . BOOT0-tied to GND by 1k resistor, BOOT1 tied to VDD by an 24k resistor NRST connected by a 100nF capacitor to GND,PDR_ON is floating. We assembled several cards: part of it operates well ,while part is not wakeup - no commination to the debugger (ST-LINK/V2 with IAR SW). I'm not sure that leaving PDR_ON floating is OK, and didn't find a clear instruction. Any help will be appreciated.

shlomo

[Tesla DeLorean]

Posted on August 02, 2015 at 21:43

Well I'm pretty sure the Data Sheet says connect it to VDD on F4 parts, quite clearly.

You'd also want to check the voltages on the VCAP pins, and the level of NRST. The POR and PLL/VCO also expect the analogue supply.

[shlomo]

Posted on August 03, 2015 at 07:44

Thanks.

The vcap pins connected to GND each by 2.2uF. The NRST rising up to VDD(3.3V) as RC rising(as expected) and - I suppose- causes a RESET during the time it's under the LO level. Is that behavior of the NRST supplies the required Power ON reset instead of the PDR_ON?

[shlomo]

Posted on August 03, 2015 at 12:27

Hi,

Following your clues, I checked the voltage on the vcap. I found that in the fault cards it was 0V. After recheck the documentation, I found that pin BYPASS_REG have to connected to GND to enable the internal regulator, while I left it floating. My mistakes was due to change an existing design from LFPQ64 package to 176 BGA package. Thanks again for the clues. Shlomo