stm32f407 USB FIFO Address

[SFrol]

Hello. I have any troubles with understanding and access to USB data Fifo's at STM32F407.

In STM32F103RBT6 (for example) it was simple - there is PMA, that starts from 0x40006000. I could directly define addresses of FIFO's for each endpoint in F103. But not in STM32F407. There is no PMA. As I understood, there is only one(!) global RX buffer and several separate TX-FIFO's for each endpoint. But where can I find addresses in memory, where can I see received or transmitted data??(with Debugger). I said, that in STM32F103 it was really clear and simple - we have PMA. But it's not works with STM32F407 (USB_OTG_FS). RM doesn't describes this clearly. I literally confused. Where is USB data-FIFO array located in F407??

[Tesla DeLorean]

I wouldn't stick the debugger over the user portions, pretty much guaranteed to fail.

One large FIFO memory region, the RX starts at the bottom and has RXFSIZ allocated to it.

There should be a debug region at +0x20000..0x3FFFF from the UBS base on the AHB

0x40040000..0x4007FFFF for USB OTG HS

0x50000000..0x5003FFFF for USB OTG FS

[SFrol]

Maybe you meant 0x2000 instead 0x20000? I see the page 1272 (Table 199) in RM. As for debugger (Keil and Atollic) used for USB, I doesn't have any troubles before (with F103 I used). It worked fine always. So I was able to see any received data in PMA through debugger.

[SFrol]

Maybe you meant 0x2000 instead 0x20000? I see the page 1272 (Table 199) in RM. As for debugger (Keil and Atollic) used for USB, I doesn't have any troubles before (with F103 I used). It worked fine always. So I was able to see any received data in PMA through debugger.

[SFrol]

Maybe you meant 0x2000 instead 0x20000? I see the page 1272 (Table 199) in RM. As for debugger (Keil and Atollic) used for USB, I doesn't have any troubles before (with F103 I used). It worked fine always. So I was able to see any received data in PMA through debugger.

[SFrol]

Maybe you meant 0x2000 instead 0x20000? I see the page 1272 (Table 199) in RM. According to RM I see that we have common buffer area for IN and OUT endpoints (0x50002000-0x50002FFC for EP 1 as example).. But.. Where is a boundary between them (IN(TX) and OUT(RX)) in this area?? (for EP 1). I still cannot understand this.

As for debugger (Keil and Atollic) used for USB, I doesn't have any troubles before (with F103 I used). It worked fine always. So I was able to see any received data in PMA through debugger.

[waclawek.jan]

> I doesn't have any troubles before

> It worked fine always.

> I was able

Forget about the USB in 'F103 - the OTG module in 'F40x (and in 'F105/107 for that matter, in 'F7 and in the higher-end 'L4) is a completely different module. Its FIFO is primarily accessed through a "mailbox" mechanism described in mentioned table 199 in RM0090 rev15. Writing to *any* word-aligned address within the given range for an endpoint will write to the Tx FIFO of given endpoint; reading is more complex due to the common Rx FIFO - packets are pushed onto that FIFO by the USB core in the order they arrive together with a header; you are first supposed to pop that header from GRXSTSP and then read the rest of the data by reading from *any* address in the whole FIFO area.

Looking at GRXSTSP and the FIFO area by debugger obviously throws off the FIFO mechanism, as the debugger reads those addresses in the same manner as the user software running in processor would. As Clive said above, there's a debug access to the FIFO's memory itself, at offset 0x20000 (yes, 0x20000) which should be non-intrusive; however, there's no access to the core's internal pointers to the FIFOs, so it's quite challenging to find out the current top of data, especally in the common RxFIFO. In RxFIFO, the data are separated by the headers (as laid out in GRXSTP). I assume you are already familiar with the mechanism to partition the FIFO area to the Rx FIFO and Tx FIFOs through GRXFSIZ/DIEPTXF0/DIEPTXFx.

JW