Posted on May 18, 2016 at 17:52Hi,
I can't get the GPIO into high speed as stated in data sheet 42Mhz with the following code even I already set the clock to Max based on Internal clock:
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
GPIO_InitDef.GPIO_Pin = GPIO_Pin_2;
GPIO_InitDef.GPIO_OType = GPIO_OType_PP;
GPIO_InitDef.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitDef.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_InitDef.GPIO_Speed = GPIO_Speed_100MHz;
//initialisation port B pins
GPIO_Init(GPIOA, &GPIO_InitDef);
while(1)
{
GPIOB->BSRRL = GPIO_Pin_2;
GPIOB->BSRRH = GPIO_Pin_2;
}
When I hooked the pin to the
oscilloscope it only
show
14Mhz, is the instruction cycle too slow to achieve 42Mhz or is the GPIO characteristic issue (rising and falling time)?
Clock setting is based on following SetSysClockInternal() function,
Clock parameters setting:
static void SetSysClockInternal(void)
{
// HSI_RC = 16Mhz
// SYSCLK = 168Mhz
// HCLK = 168Mhz
// APB1 peripheral = 42Mhz
// APB1 timer = 84Mhz
// APB2 peripheral = 84Mhz
// APB2 timer = 168Mhz
__IO uint32_t HSIStatus = 0;
/* Enable HSI */
RCC->CR |= ((uint32_t)RCC_CR_HSION);
/* Wait till HSI is ready and if Time out is reached exit */
do
{
HSIStatus = RCC->CR & RCC_CR_HSIRDY;
} while(HSIStatus == 0);
/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSI) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
}
regards,
David
#stm32 #internal-clock #gpio
