Stm32F407 Clock Configuration Issue

[RGokm.1]

Hi,

I am working on my Stm32F407 Discovery Board. I use CMSIS when I codding and I have some problems with PLLCFGR register. I want to using 168 mhz clock speed. This is my Clock Configuration code and I get problem in PLLM configuration in PLLCFGR register. PLLM value does not change. I want to set 8 but it still 19.

And we come to the most interesting part. I was try my clock configuration in Cubemx. Then I run Cubemx's code and it works! All register value is as I want. I save ALL CLOCK register values from Atollic's SFR page and write to registers with CMSIS code. But I still get wrong PLLCFGR value. This clock configuration working on CubeMx but doesnt work on CMSIS!! I dont understand it.

        RCC-> CFGR		|= 0x4008940A;
	RCC-> PLLCFGR 	 = 0x00000000;
        RCC-> PLLCFGR	 = 0x00000008;			//PLLM 8
	RCC-> PLLCFGR	|= 0x00400000;			//PLL Source is HSE
	RCC-> PLLCFGR 	|= 0x00005400;			//PLLN 336
	RCC-> PLLCFGR	|= 0x04000000;			//PLLQ 4
	RCC-> PLLI2SCFGR|= 0x50003C00;
	RCC-> CR		|= 0x00010000;			//HSE On
	RCC-> CR		|= 0x01000000;			//PLL On
	RCC-> CR		|= 0x04000000;			//PLLI2S On
 
	RCC-> AHB1ENR	|= 0x00000080;			//GPIOH Clock Enable For HSE Crystal
 
	RCC-> AHB1ENR 	|= 0x00040000;			//Backup SRAM Clock Enable
 
	RCC-> APB1ENR   |= 0x10000000;			//Power Interface Clock Enable
 
	PWR-> CR		|= 0x0100;				//Backup Access Enable
 
	RCC-> APB2ENR	|= 0x00004000;			//System Configuration Controller Enable

[Tesla DeLorean]

Seems to be rather an inefficient coding style.

Need to be sequenced, HSE needs to be running before you use it, PLL need to lock before you switch to it. Surely this is described in RM

Might want to look at the examples in the SPL

[RGokm.1]

Yes you are right. This is inefficent way. But this one just trying for right clock configuration. I was made what you say. Firstly start HSE, wait HSE ready flag, etc. And I was find this paragraph in RM about PLL configuration. But my code already same this paragraph. I was adjust PLLM,N,Q and then I start PLL. But I still cant change PLLM bits. But CubeMx still can doing this!! I dont understand.

[Tesla DeLorean]

can't change PLL settings while running, ORing bits on won't clear bits you need cleared​

[RGokm.1]

I found my Issue where did came from. system_stm32f4xx.c and stm32f4xx.h files need changes for Stm32f4 Discovery board. This codes writing for 25Mhz HSE crystal but Discovery Board has 8Mhz HSE crystal. Then PLL bits. These bits defined in system_stm32f4xx.c file. You must be change PLL bits as you want. Thanks all of us;)