Hello Community,
I am struggling to get a retriggerable one pulse mode working on a STM32F405 and I reached the point where I am not sure whether this is actually possible with the processor. I saw that newer processors have the "Combined Reset Trigger Mode" option which I think is not available for the STM32F405.
As this not available in hardware I think I have to reset/reconfigure the timer by software such that it can be retriggered after the One Pulse mode was executed.
I want to have 3 cascading timers, namely 2, 1 and 3 where timer 2 gets triggered from the outside via ETRF and timer 1 gets triggered via ITR1 and timer 3 gets triggered via ITR0.
This should look like the following:
As in the picture, I am able to configure the timers as described and trigger the cascade once.
Then I read in the manual, that I need to "Write TIF = 0" and this is where I am stuck.
My understanding of "Write TIF = 0" is that I need to reset the status register:
TIMx->SR = ~TIM_FLAG_Trigger;
But that does not seem to be enough to "arm" the timers again.
I have tried resetting all interrupt bits in the SR registers and generating an update event with
TIMx->EGR = TIM_EGR_UG;
and many more variants but I was not able to retrigger the timers.
Any help on what I am missing to make the timer cascade retriggerable or what is meant "Write TIF = 0" is welcome.
Also whether it is at all possible what I am trying to realize with the STM32F405.
Some background to my project:
The 3 pulses shall be retriggered constantly to form a sort of PWM signal. But the duration between the pulses varies slightly s.t. I can not use the PWM mode, especially because sometimes the duration is shorter than the period of one PWM cycle.
All of this happens at 100kHz that is why I was not able to just adapt the ARR and CCR registers with software via an ISR. I get a flickering as some other ISRs seem to sometimes delay the ISR.
My hope is that resetting the timer is not causing unwanted flickering as the reset itself is not so time critical.
Thank you everybody
Luke
Hi JW,
thanks for your quick reply.
That is what I am trying to do. I can trigger Timer 2 via ETRF:
(yellow is my signal via ETRF and cyan is TIM2)
and I can also do this multiple times:
I am also able to trigger the cascade once:
(yellow: ETRF, cyan: TIM2, pink: TIM1, blue: TIM3)
But after I triggered the cascade once, I can not do this again, but instead the result looks like in figure 1 and 2.
I get exactly the same result when I trigger TIM2 via:
TIM2->CR1 |= TIM_CR1_CEN;
But my understanding of the slave mode controller is that is "just" setting the CEN bit anyways.
So my shortcoming is definitely, that I am not able to make TIM1 and TIM3 retriggerable via the internal trigger connection.
As the ETRF PIN gets set to low and again to high from the outside and this allows me to retrigger TIM2,
I feel like I am missing this exact point in the internal trigger connection of setting the respective bit to low.
So basically I think I need to set ITR0 and ITR1 to low but here I am having problems of understanding the underlying concept.
My understanding is that the TIF bit in the status register of the respective timer gets set to high when the selected ITRx source is getting fired. I have set e.g. for TIM1
TIM_SelectInputTrigger(TIM1, TIM_TS_ITR1); which sets the SMCR register.
And then I need to reset the TIF bit in the status register.
But setting TIMx->SR = 0; does not do the job.
So I figured I need to do some preliminary steps or followup steps to write to the status register or make the timer load the status register.
But here I do not know what to do, so any help would be appreciated.
I have tried already to disable and enable the preload register with
TIMx->CR1 &= ~TIM_CR1_UDIS;
and also to generate an update event with
TIMx->EGR = TIM_EGR_UG;
But none of these seemed to help.
Is there any necessary step to write to the status register?
Also is my understanding of the concept of the internal trigger connection somewhat correct?
Thank you for your help:)
