STM32F4 does not self-reset on power up; BOOT0 is tied to GND

[geof]

Posted on April 16, 2013 at 22:58

Hello,

I'm using an STM32F415 in an LQFP64 package on a new PCB design. BOOT0 is tied to ground. I can program the STM32 (using IAR and the ISP designed by ST) and get it to run using the IDE. The NRST pin is floating on the PCB, though connected to the JTAG of course. However when I remove the ISP the processor no longer resets on it's own. I can, though, get the processor to run by shorting NRST to GND. I am pretty sure this is something to do with the PCB design itself- I have another ''old'' PCB design, also using the same processor, and some code that runs fine on that old PCB design. (e.g. it resets on it's own just fine.) But when I take that known code and program it into the new PCB design I get the same result- it runs when the ISP is connected and prompted in the IDE, and runs when I manually short the NRST to GND, but does not reset to start running on it's own. I have already fabricated a second of the ''new'' PCB designs to rule out a bad processor. Same result. I even tried physically desoldering and bending up the NRST pin to eliminate the possibility of capacitive (or whatever) loading on that pin. Same result. I do have the requisite 0.1uF bypass capacitors, 2.2uF regulator capacitors for VCAP, and 4.7uF big bypass capacitor, and VDDA and VSSA are connected respectively to VDD and GND. This is for both the troublesome ''new'' and verified ''old'' PCB designs. BOOT0=GND on both designs. Has anyone experienced something like this before, or have any suggestions? Thanks! Geof

[Tesla DeLorean]

Posted on July 28, 2015 at 17:31

I don't know, and haven't looked. Are you driving the NRST pin externally?

[pavel]

Posted on July 28, 2015 at 17:35

Hi, Clive, no, nRST pin is not externally control.

[Tesla DeLorean]

Posted on July 28, 2015 at 17:40

And you have the scope in persistence mode so you can see this, or using a logic analyzer?

[pavel]

Posted on July 28, 2015 at 17:54

I have oscilloscope on this pin, in single mode, RUn mode all modes on oscilloscope I try to set, but never time I can not see pulse on this pin, whe uP wake up from STANDBY.

But in doccumntation is mentioned ''After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).'' wake up from stand by is same as RESTART ... wen I restart uP there is pulse on nRST ''1''''0''''1'' and flag PINRSTF is set. But when I wake up from  STANDBY mode no pulse on nRST and no PINRSTF set ''0''.

[Tesla DeLorean]

Posted on July 28, 2015 at 18:19

My experience is that I can read PWR_FLAG_SB and determine that I restarted out of a STANDBY state.

I don't really know enough about your design or test methodology to understand what's going on in your situation.Pulling as single 20us pulse out of a period of several seconds is going to be fun on a scope.

[pavel]

Posted on July 28, 2015 at 20:40

Situation is that according to documentation nRST pulse have to be propagated out by nRST pin and set flag in  PINRSTF.

You can see

Figure 15. Simplified diagram of the reset circuit. - you can check this circuitry

According this chapter Power rest, flag PINRSTF is set  and pulse 20us when: WWDG reset IWDG reset Power reset Software reset Low power management reset and pulse is propagatet out of NRST pin. Becase in case of  WWDG reset, Software reset, flag is set, and pulse propaged out of chip on my desk. But when i set uP to STANDBY, uP wake up without PINRSTF flag and pulse on nRST pin appears.

6.3.21 RCC clock control & status register (RCC_CSR)

 

Address offset: 0x74

Reset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only

Bit 26

PINRSTF:

PIN reset flag Could you please chck, if when you uP STANDBY and wake up, will be set flag PINRSTF and puls e on pin?

[Tesla DeLorean]

Posted on July 28, 2015 at 21:03

Could you please check, if when you uP STANDBY and wake up, will be set flag PINRSTF and pulse on pin?

I really can't commit my resources to validating your assertion.My notes indicate that RCC_FLAG_PINRST (Bit 26) is always set, so you have to test PWR_FLAG_SB first. At least on my hardware. Do you have an external pull-up, and are you doing this outside the debugger?

[pavel]

Posted on July 29, 2015 at 08:00

I have circuitry where is pin nRST connected to pull-up resistor.

When I call soft restart pin go ''1''''0''''1''and flag PINRST  is set When I call STANDBY, nothing pulse on pin still stay in ''1'' and flag PINRST is not set. My device is batery device and in STANDBY is power for uP still ''ON'' uP. But uP really in STANDBY mode, because I wake up u P when I connect there external power supply. But without action on pin NRST and flag. I will check flag PWR_FLAG_SB, like you mentioned. But I do kot know why flag PINRST  is not set, when in ST doccumentation is claimed, that when up wake up from STANDBY this flag is set and puls is on pin nRST. May be some failure in ST doccumentation ...  I do not know.

[Amel NASRI]

Posted on July 29, 2015 at 17:36

Hi spata.pavel,

In RM0090, we have the following description for PINRST (This bit is set by hardware when a reset from the NRST pin occurs.). I don't see where exactly the documentation says ''when up wake up from STANDBY this flag is set and pulse is on pin nRST''?Have I missed something.-Mayla-

[pavel]

Posted on July 31, 2015 at 08:46 Hello Mayla, according to me, it is mentioned in documemntation (RM0090). 6.1.2 Power reset A power reset is generated when one of the following events occurs: 1. Power-on/power-down reset (POR/PDR reset) or brownout (BOR) reset 2. When exiting the Standby mode A power reset sets all registers to their reset values except the Backup domain (see Figure 4) These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map. The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low. Figure 15. Simplified diagram of the reset circuit The Backup domain has two specific resets that affect only the Backup domain (see Figure 4).

2. When exiting the Standby mode

A power reset sets all registers to their reset values and reset value for register 6.3.21 RCC clock control & status register (RCC_CSR) Address offset: 0x74 Reset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. and

0x0E00 0000

it means that bit26 of PINRST will be SET. Is it correct or not? When you wake up uP from STANDBY, your biy26 a and PINRST pulse or not? Thank you Ptavel