The RM0090 Reference manual (DocID018909 Rev 10) mentions on p310 that :
When the data width (programmed in the PSIZEor MSIZE bits in the DMA_SxCR register)
is a half-word or a word, respectively, the peripheral or memory address written into the
DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word
address boundary, respectively
However the AN4031 Application note mentions p9:
A DMA transfer is defined by a source address and a destination address. Both the source
and destination should be in the AHB or APB memory ranges and should be aligned to
transfer size
Anyone any insight into that ? Alignment to the transfer size seems strange ?
