STM32f4 Discovery ADC problem

[SMitr]

I am trying to do a partial integration on a 550 KHz waveform using STM32F4 Discovery board using the Waijung toolset in Simulink. The sampling time that I am using is 0.018 us, i.e 3 cycles if the clock frequency is 168 MHz. The ADC prescaler is 2, so the ADC frequency is 84 MHz. The total time required for the conversion should be 0.143 us (12 bit resolution) +0.018 us i.e. around 0.16 us. This should theoretically suffice the Nyquist criteria for sampling. However, I dont seem to get any output at the end. I can't see the real time data after ADC, using the serial interface or the DAC. So I am not sure what I am doing wrong. Any suggestions or ideas is much appreciated.

P.S. I am attaching the waveform I am trying to acquire (integration between say 20 us to 140us) and the simulink program. Please let me know if any other information is required.

[AvaTar]

> The sampling time that I am using is 0.018 us, i.e 3 cycles if the clock frequency is 168 MHz.The ADC prescaler is 2, so the ADC frequency is 84 MHz

I don't think so. 84 MHz is far beyond the max. ADC clock, check the datasheet.

Not to mention, 12 MByte/sec is a bit beyond the UART capabilities, and the DAC has settling times of a few microseconds.

[SMitr]

​According to the clock config file, PCLK2 is 84 MHz by default. So if I consider another prescaler of 2 after this, the frequency would be 42 MHz (the datasheet says Fplck2/prescalar). I understood that the UART or the DAC wouldn't work, but I was trying whatever I could. My main motivation is to get the digital output that I am trying to obtain after the integration of the curve and the comparator. With the 42 MHz frequency this should be at least achievable, isn't it?

[AvaTar]

Not sure if we speak about the same device.

[AvaTar]

And not sure either why the forum editor does not show my image.

[SMitr]

I was referring to the Reference Manual, but I also found the one you are talking about. Seems like making the ADC work at that frequency will be a stretch. With a single ADC, there will only be around 3-4 samples per cycle at a data rate of 2 MSps. Although it still suffices the sampling criteria​, do you think practically getting the data out contnuously at that rate is feasible? Sorry I haven't got much experience with this, so would gladly like to hear some views.

[Tesla DeLorean]

Well you could certainly sample at the limits of the ADC, but you'd need a deep enough buffer to decimate the interrupt loading, because you've really want that below 100 KHz, and perhaps much slower if you plan on doing a lot of math/processing on the data.

[AvaTar]

And getting out 3 samples at 2 Msps would mean about 12 MBps, meaning approx. 120.000.000 bps for the UART (assuming 10 bits per byte).

And as Clive mentioned, processing 3..4 values at that sample rate in real-time is ... at least a challenge.

Consider a real DSP with the ability to execute several instructions at once. These devices are made for a considerable instruction load in tight interrupt loops.

[SMitr]

Thank you everybody for the insights.​