STM32F373CCT6 SPI issues

[jprinster]

Posted on May 16, 2014 at 17:55

I am having issues with SPI1 and SPI2 on the STM32F373CCT6 chip.

1) I have both busses configured the same as full duplex, 16 bit data, master mode, baud rate scaler of 8.  However, when I look at the SPI clocks on a scope or logic analyzer they are different.  Is there some other setting that is causing this?

2) SPI2 seems to work just fine.  When I send data to the slave the clock shows 16 pulses.  However, when I do the same thing with SPI1 I get 17 pulses.  What could cause this?

3) I am using SPI1 to retrieve data from a TI ADS8866 ADC.  That device is trigger by an IO pin and then it transmits data on the master's clock.  With the SPI1 set up as full duplex, since this is a read-only device if I use the library function to read a 16 bit data, the SPI1 CLK does not produce any clock signals to retrieve the data.  I have had to resort to doing a write operation so the SPI1 generates the clock pulses (however it sends 17 pulses as I mentioned above).  Is there a command for reading that will cause the clock to be generated?  I don't want to configure it as RxOnly since that turns the clock on all the time and I have no way of turning it off after 16 pulses.

Thanks,

Jim

#stm32f373cct6-spi

[Tesla DeLorean]

Posted on May 16, 2014 at 18:13

1) I have both busses configured the same as full duplex, 16 bit data, master mode, baud rate scaler of 8.  However, when I look at the SPI clocks on a scope or logic analyzer they are different.  Is there some other setting that is causing this?

How are they different? The rate, the waveform? Noticed on had 16/17 clocks. What's the bandwidth of the capture tool? One SPI is on APB2 the other on APB1, and THOSE buses are clocked at different rates, perhaps 72 MHz and 36 MHz respectively, or however you have them set up.

[jprinster]

Posted on May 16, 2014 at 18:20

The frequencies are different.  But as you further explained about the different bus clocks, that would explain it.  I'd forgotten about that. 

Thanks.

[os_kopernika]

Posted on May 16, 2014 at 22:55

Ad2. I suspect that:

If SPI is configured as master, it drives IOs in HZ allowing other SPI masters to actively control the bus. As soon as it has some data to transmit, SPI overtakes control over SCK and MOSI (here it depends on OTYPER). After the transmission completes these lines go HZ. So, you have the clock idle low and a pullup or clock idle high and pulldown on SCK. After transmission the pull-up/down does the 17-th clock edge.