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STM32F373CCT6 2 Channels Single ended wired together for 16 bit ADC interleaved 50 KHz to 100 KHz , Can it be done with 2 Differential channels at same speed 50KHz to 100KHz or is it stuck at 16Khz max speed in differential mode

MKing.2364
Associate III

Device STM32F373CCT648 pin

We currently using 2 single ended 16 bit SADC inputs one on SADC1 PE9 and one on SADC2 PB2.

We interleave the two 50KHz single channels using a 10uS delay between them. This uses DMA SADC transfer an interleaves the signal to achieve a 100 KHz sampling rate needed for our niche application.

The two inputs pins PE9 and PB2 are tied together to the output of our signal op amp the opamp has one output wired to both the PE9 and PB2 pins.

The single opamp has two wave forms in the same signal they are separated by an index pulse to separate the sampling into 2 bins one for the ref and one for the sample part of the waveform.

The system works great, the 100 KHz oversampling increases the resolution of the system by oversampling.

Were are making an new version of the design with a different detector sadly the SNR is lower.

We want to use two channels again of the SADC1 and SADC 2 but this time using differential mode as this increases performance common mode rejection.

This means we need 4 pins of the micro as differential requires 4 pins.

We choose PB0 & PB1 SADC1 and PE8 & PE9 SADC2

We want to wire the plus inputs together so PB0 and PE8 differential plus inputs go to the op-amps output

We will wire the - inputs to the Analogue Gnd 0V to pins PB1 and PE9

in single ended mode we run in fast mode 6Mhz SADC clock to get 50 Khz interleaved to get 100 KHz sampling rate

IN differential mode I here the Max Sampling rate is 16.3Khz is this true? Or can it run at the full 50 KHz in Differential Mode.

1) Will the differential mode only support 16.3Khz max sample rate??

Does this mean interleaved we can only get 16.3 KHz * 2 = 32.6 KHz max sampling rate

Or can they run at 50 KHz * 2 = 100 KHz they work fine in singled ended mode at this max sampling rate when interleaved.

2) is it okay electrically to tie the two minus PB1 and PE9 together to Analogue Gnd

and tie the two plus inputs together PB0 and PE8 together to the amplifiers output

This is rather a hardware question of the STM32F373CCT6 max sampling rates we can handle all the software at our end

Many thanks

Matthew King

Electronics Hardware Engineer

8 REPLIES 8
Chris Lynch
Associate III

Mathew,

Have a look at reference manual RM0313 page 230 onwards.

MKing.2364
Associate III

Dear Chris,

Many thanks for your kind reply .

I have had a good read of the RM0313 STMF373xxx Programming reference manual

What is unclear is whether, when used in differential mode this counts as multiple channels 16.6KHz or counts as single channel (50 KHz)

Does the SADC measure the top and bottom pin of the differential input pair = 2 pins and takes 2 measurements does this decrease the speed from 50Khz to 16.6Khz or does it just measure the voltage across the two pins and counts as a single channel?

Also my other question,

Our current design uses single ended mode we tie two Input pins together SADC1 PE9 and SADC2 PB2, We interleave at 50 KHz injecting a 10uS delay between them this gives us solid 100Khz sampling rate, Using Interrupt and DMA Transfer uses CUBE MX driver. 16Bit SADC & DMA Transfer

The sampling array is interleaved PE9 A PB2 B, A,B,A,B all way down to get 1000 16 bit ADC measurements for the 10mS signal were measuring, They are all added together to get a huge number which is then filtered and averaged

Can 2 differential channels be wired together tops wired to op amp output bottoms joined to Analgue 0V of OP-Amp in the same way ??

PB0 >DIf top ++++++++

PB8 > DIf top +++++++

PB1 DIf bottom -------

PB9 bottom -----------

I need to know this before I can commit to laying out the new 4 Layer PCB also does STM32 allow interleaved method with 2 x differential channels it works great in single ended mode and doubles our speed from 50Khz to 100Khz

Out niche application requires fastest sampling possible as it increases system resolution by oversampling theorem

Here is a snippet from page 231

Is it 50Khz or 16.6Khz for a differential channel
_legacyfs_online_stmicro_images_0693W00000bkurCQAQ.png 

Kind regards

Matthew

AScha.3
Principal III

you can get 50ks from one ADC - single or diff. input .

so using 2 ADCs in interleaved mode can make 100ks , also on diff. inputs.

just look, whether there is some "extra" limit on some channels (some have "slow" or "fast" name) and choose the best on each ADC (if there are slow--fast on this chip).

+

you can put inputs together as in single ended in, just respect the common mode input range (see in ds )

 
_legacyfs_online_stmicro_images_0693W00000bkvMJQAY.png+

as you can see (15.3 sdadc...) each ADC has its diff/input mux in front:


_legacyfs_online_stmicro_images_0693W00000bkvLRQAY.png

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MKing.2364
Associate III

Dear AScha 3,

Many many thanks for your kind reply and taking the time to help.

This is excellent news, we can now carefully check which channels have fast rather than a slow name we will chose two differential inputs which have a 'Fast Name'

Brilliant new you can get 50KHz from one SADC whether in single or differential mode

And using two ADC's in interleaved mode we can make 100 KHz on two interleaved differential inputs that is the best news thank you for explaining it to me.

We will ensure the signal respects and is within the common mode input range we will scale our amplifiers output to ensure it is within the common mode input range for the differential pair

many many thanks this ids great news for a Friday.=)

I shall now study your post, the Rm3013 ref manual and the STM32F373CCt6 data sheet in great detail to make sure we choose two fast channels for these 2 x differential pairs which we be interleaved at 100 KHz

Thank you so much again for sharing your time and knowledge with me.

Kind Regards,

Matthew

Chris Lynch
Associate III

Mathew,

I was just about to post the same image as Ascha, there seems to be a differential amplifier/gain stage just before the ADC, see page 233 of RM0313.

As long as your only measuring a single channel in continuous mode on each SDADC then it should be able to measure 50kHz. (which you are)

See page 240 of RM0313, section 13.5.9 for the FAST bit to enable 50khz sampling.

You should try and use STM32CubeIDE or STM32CubeMX to explore channel selection for the SDADC, there is also a dropdown for FAST conversion mode when continuous mode is enabled.

Chris

good...and i see on quick look at rm no fast/slow channels, only (fast) SAR ADC seem to have such.

see input mux for a channel, always +/- inputs there, can only choose to use them or leave one input at gnd -> single ended then.

so anyway inputs have diff. input stage:


_legacyfs_online_stmicro_images_0693W00000bkvdeQAA.png 

and look for optimum ground ...->


_legacyfs_online_stmicro_images_0693W00000bkvdFQAQ.png 

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Dear Chris,

Many Thanks for your extremely technical reply.

I have a dev Kit with the STM32F373CCt6 on it with all headers for each pin,

I will play with the Cube MX and Cube IDEA I use both tools regularly,

I will wire a POT up at mid signal and try it

I will get back to you when I have it working maybe middle of next week its quite a lot to check and setup.

Thanks Again Chris

Regards,

Matthew

Dear Ascha.3 many thanks I will read and study Section 6.1.2 Correct Grounding for Analog applications


_legacyfs_online_stmicro_images_0693W00000bkvkLQAQ.png
_legacyfs_online_stmicro_images_0693W00000bkvkGQAQ.png