2017-04-17 10:36 AM
Hi,
While trying to calibrate the RTC on the F334, tripped on this rather possible bug..
I guess this is a bug in the Application Note AN3371
Doc ID 018624 Rev 5
Figure 11. Smooth calibration block, the RTCCLK is assumed to be 32768,
as well as in
Figure 18. RTC_CALIB clock sources
Just above Fig 18, it also states:
Setting 1 Hz as the output signal
1. Select LSE “32768 Hz� as the RTC clock source.2. Set the asynchronous prescaler to the default value “128“.3. Set the synchronous prescaler to the default value “256“.4. Enable the output calibration by setting “COE� to ‘1’.5. Select 1 Hz as the calibration output by setting CALSEL to ‘1’.But, according to the datasheet RM0364, DocID025177 Rev 2
RTC prescaler register (RTC_PRER)
Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor
This is the asynchronous division factor:ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)Bit 15 Reserved, must be kept at reset value.Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factorThis is the synchronous division factor:ck_spre frequency = ck_apre frequency/(PREDIV_S+1)Asynchronous prescaler is 7 bits wide. Setting '128' will overflow the bitfield, but setting 127 (0x7f) does seem correct.
But, 32768/128 = 256Hz, but the figure states 512Hz.
Isn't this a bug in the document ? Is there an already update to the Application Note already available ?
Thanks.
2017-04-20 12:33 AM
Table 3 uses '127 (div128)', and 'divXXX' is used on many places of the AN.
Not a bad idea, but shall be explained in the AN's introduction, and then be used consistently - there are many places where the divider is used without the 'div' prefix (including the figures).
ST, please comment.
JW
2017-04-21 09:33 AM
Hi
Abraham.Manu
,Waclawek.Jan
,I want to thank you for your contribution. This is helpful for us to improve our doc offers.
I will raise your feedback internally.
Imen