STM32F303R8T6 Bit-Banding Calculation Out of Range

[BG1]

Hi , I encountered an interesting problem while I was trying to calculate the Bit-Banding Address of GPIO registers .

The peripherals working on AHB2 and AHB3 busses are overflowing when trying to calculate their bit-banding map .. For Example ;

I wanted to ease the syntax of reading some IO pins and here is the result for GPIOA , IDR register..

--------------------------------------------------------------------------------------

PERIPH_BASE =0x40000000

Address offset of IDR is = 0x10

AHB2PERIPH_BASE=(PERIPH_BASE + 0x08000000)

GPIOA_BASE =(AHB2PERIPH_BASE + 0x00000000)

GPIOA_BASE=0x48000000

---------------------------------------------------------------------------------------

For GPIOA_IDR_Bit0;

GPIOA_IDR_Bit0=0x42000000 + ((GPIOA_BASE +0x10-0x40000000)*0x20);

GPIOA_IDR_Bit0=0x142000200 .... Which is out of 0x42000000 -- 0x43FFFFFF Range !

Is there something I misinterpret ? or This is the reality of bit-banding exception such that doesn't work on some peripherals ... ?? Please tell me the truth .. I can live with that :)

[waclawek.jan · Accepted solution]

AHB2 and AHB3 is not within the bit-banded peripheral area, which is 0x40000000-0x400FFFFF. See Bit-banding chapter in PM0214.

JW

[BG1]

So I have to go with RMW instructions for bit operations ? No other chance ?

[waclawek.jan]

No, but for example GPIO has it's own atomic write register, BSRR.

JW

[BG1]

Can you give me an example ?

[Tesla DeLorean]

GPIOA->BSRR = 0x00000001; // Set bit 0 (PA0)

GPIOA->BSRR = 0x00010000; // Clear bit 0

or *((uint32_t *)&GPIOA->BSRR) on platforms where BSRR/BRR are split in the structure definition

*((uint32_t *)&GPIOA->BSRR) = 0x00000001; // Set bit 0 (PA0)

*((uint32_t *)&GPIOA->BSRR) = 0x00010000; // Clear bit 0

[BG1]

Thank you so much Clive !