cancel
Showing results for
Search instead for
Did you mean:

# [STM32F3] HSE crystal selection, confused by AN2867

Associate II

I'm trying to select a suitable HSE and size the capacitors + resistor for it following the procedures laid out in AN2867, but I can only reach a "not compatible" result even with the example values used in there (the different stages are done for different crystals in the document).

I'm looking whether I could use a 12MHz crystal with 20pf load capacitance 7pf shunt capacitance and 80 Ohm ESR, but I don't seem to get the procedure fully..

I understood it like this:

1. Calculate the required load capacitor values based on crystal load capacitance and estimated stray capacitance
2. Calculate gain margin based on microcontroller transconductance, crystal frequency, load capacitance, shunt capacitance and ESR, making sure it is >5
3. Calculate the required series resistor value based on the load capacitor value chosen earlier
4. Re-check that the gain margin is still >5 by adding the resistor value to crystal ESR and recalculating it

In the different examples they don't use the same crystal, for the stray capacitance they use one with 15pf load capacitance, and gain margin is calculated for another with 10pf.

For example, the example calculates a gain margin with Cl (frequency) 8MHz, load capacitance 10 pf, shunt capacitance 7 pf, ESR 80 and microcontroller transconductance 25 for an F1 processor, and end up with a value of 107, which easily satisfies the >5 criteria.

Then, the equation for load capacitors with the 10pf load capacitance crystal with assumed 5 pf stray capacitance gives a value of 10pf.

Then, calculating the external resistor for this crystal based on those values using  RExt = 1 / (2 π F CL2) gives ~1990 ohms.

Adding that resistor value to the gain margin equation like shown in the example completely dominates the ESR of the crystal (80), ending up with a gain margin of 4.16 which fails to satisfy the >5 condition. For a F3 processor with lower transconductance, the results are not even close. Since I assume the crystals used in the examples should work with these chips, I must be doing something wrong.

What am I missing in this procedure?

2 REPLIES 2
Lead

its very hard to make a crystal circuit fail, just follow the suggested circuit in the datasheet

probably the lowest "power and noise" possible if you tune in the capacitors and PCB tracks 100%.

most processors don't need a crystal anymore.

did you look at alternatives ?

Associate II

The app note does stress the importance of picking the right capacitors and whatnot to prevent issues. I am using the suggested circuit, just trying to choose the component values. I'd like to at least understand why the examples provided appear to lead to a completely unworkable solution (gain margin less than 1, should never even work?), I must be doing something wrong.