Posted on September 07, 2016 at 11:54Hi,
Now I already can set up lcd, can send some setting cmd......
I base on example from ST, it build for stm32f103z..... But it using DMA for FSMC, and look DMA of stm32F1 and F2 alot different.
Could you tell me how to change DMA from F1 to F2, for current code is:
/**
* @brief LCD_DriverDMAConfig
* DMA channels configuration to send data to FSMC TFT-LCD.
* @param None
* @retval None
*
*/
static void LCD_DriverDMAConfig(void)
{
/* Configure clock for DMA Controller */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1,ENABLE);
/* Deintialize DMA Channels */
DMA_DeInit(DMA1_Channel1);
DMA_DeInit(DMA1_Channel2);
DMA_DeInit(DMA1_Channel3);
/* DMA1 Channel1 Configuration for line front porch */
DMA1_Channel1->CCR &=((uint32_t)0xFFFFFFFE);
DMA1_Channel1->CCR &= ((uint32_t)0xFFFF800F);
DMA1_Channel1->CCR |= DMA_DIR_PeripheralSRC| DMA_Mode_Normal |
DMA_PeripheralInc_Disable | DMA_MemoryInc_Disable |
DMA_PeripheralDataSize_HalfWord | DMA_MemoryDataSize_HalfWord |
DMA_Priority_High | DMA_M2M_Enable;
DMA1_Channel1->CNDTR = LCD_LINE_FRONT_PORCH;
DMA1_Channel1->CPAR = (uint32_t)DummyDisplayBuffer;
DMA1_Channel1->CMAR = (uint32_t)(LCD_BASE);
/* DMA1 Channel2 Configuration for valid line data */
DMA1_Channel2->CCR &=((uint32_t)0xFFFFFFFE);
DMA1_Channel2->CCR &= ((uint32_t)0xFFFF800F);
DMA1_Channel2->CCR |= DMA_DIR_PeripheralSRC| DMA_Mode_Normal |
DMA_PeripheralInc_Enable | DMA_MemoryInc_Disable |
DMA_PeripheralDataSize_HalfWord | DMA_MemoryDataSize_HalfWord |
DMA_Priority_High | DMA_M2M_Enable;
DMA1_Channel2->CNDTR = LCD_HORZ_LINE;
DMA1_Channel2->CPAR = (uint32_t)DummyDisplayBuffer;
DMA1_Channel2->CMAR = (uint32_t)(LCD_BASE);
/*DMA1 Channel3 Configuration for back porch data*/
DMA1_Channel3->CCR &=((uint32_t)0xFFFFFFFE);
DMA1_Channel3->CCR &= ((uint32_t)0xFFFF800F);
DMA1_Channel3->CCR |= DMA_DIR_PeripheralSRC| DMA_Mode_Normal |
DMA_PeripheralInc_Disable | DMA_MemoryInc_Disable |
DMA_PeripheralDataSize_HalfWord | DMA_MemoryDataSize_HalfWord |
DMA_Priority_High | DMA_M2M_Enable;
DMA1_Channel3->CNDTR = LCD_LINE_BACK_PORCH;
DMA1_Channel3->CPAR = (uint32_t)DummyDisplayBuffer;
DMA1_Channel3->CMAR = (uint32_t)(LCD_BASE);
/* Enable DMA Channel1 Transfer Complete interrupt */
DMA1_Channel1->CCR |= DMA_IT_TC;
/* Enable DMA Channel2 Transfer Complete interrupt */
DMA1_Channel2->CCR |= DMA_IT_TC;
/* Enable DMA Channel3 Transfer Complete interrupt */
DMA1_Channel3->CCR |= DMA_IT_TC;
}
/**
* @brief LCD_DriverInterruptConfig
* Configures the used IRQ Channels for TFT-LCD driver
* @param None
* @retval None
*
*/
static void LCD_DriverInterruptConfig(void)
{
/* Configure the Priority Group to 2 bits */
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_3);
/* Enable the DMA1 channel1 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel1_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
/* Enable DMA1 channel2 IRQ Channel */
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel2_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
/* Enable DMA1 channel3 IRQ Channel */
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel3_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
/* Enable the Frame Rate Control, TIM3 global Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
/* Enable the SlideShow , TIM2 global Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
/* Clear TIM2 update interrupt pending bit */
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
/* Clear TIM3 update interrupt pending bit */
TIM_ClearITPendingBit(TIM3, TIM_IT_Update);
}
Does DMA1_Channel1 of F1 is DMA1_Stream0 of F2.....?
Regards
Thinh