STM32F103C8T6 SPI problem

rahulnadgouda · ‎2011-08-31

Posted on August 31, 2011 at 15:16

Hi,

I am trying to establish communication between STM32F103C8T6 and an ASIC using SPI.The STM32 is the master and the ASIC is the slave. The requirement of the ASIC is that it requires the MOSI line to be high during idle(i.e the MOSI line should have an high state before clock appears on the SCK line).I have added pull up resistors of 4.7kohms on MISO,MOSI and SCK lines. I am not using NSS pin. Here are my observations:

1. The MOSI line latches to either high or low value which is dependent on the data shifted through the buffer.

2. When I set the SPE bit(SPI enable bit) in SPI CR1 register, the MOSI line is pulled low .The pin is configured as Alternate function output(observed in push pull as well as open drain).

I have verified the other settings.

Please help me out people, this is really very urgent.

Regards

Rahul

#stm32-spi

rahulnadgouda · ‎2011-09-01

Posted on September 01, 2011 at 21:27

Hi John,

Yes i was working on the same solution. Unfortunately after i reset SPI (by resetting the SPE bit) and enable it again then it pulls the MOSI line low for about 500 ns before outputting clock and data.

Regards

RAhul

rahulnadgouda · ‎2011-09-01

Posted on September 01, 2011 at 21:42

Hi Clive,

That's why I said to mux the clock off the pin. Try setting the pin for GPIO output or input, rather than connected to the SPI peripheral. You could try switching the data to GPIO INPUT PULLUP.

Yes I have tried that way. The moment data is pushed into data register and if the SPI is configured as Master with the SPI Enable bit set, clocks are generated to push the data out.

So i tried a different way.

I disabled SPI so that the MOSI line got pulled high. Then i pushed data in the data register (but spi is still disabled). Then i enabled SPI(so that the line wont go low and the since the data register has data so ideally SPI engine should output data at the same instant without pulling the MOSI line low)

But what it actually does is it outputs data and clock 500 ns after i have enabled SPI and it pulls down the MOSI line for those 500 ns.

Regards

Rahul

John F. · ‎2011-09-02

Posted on September 02, 2011 at 09:10

I wonder if the pin is always briefly pulled down - even if the GPIO data registers are set to output 1 (They will have been cleared to zero by RESET). Anyway, Clive1 already gave you the solution - bit banging ...

''What would it take? 10-20 minutes, and confirm that communication with the ASIC is viable. I'd take that route rather than scratch/bang my head for two hours and make no progress.''

It may not be pretty or cute but it will work and could realistically be coded in the time suggested.

emalund · ‎2011-09-02

Posted on September 02, 2011 at 21:37

communication between STM32F103C8T6 and an ASIC using SP

two wrongs do not make a right. The fact that the ASIC can not handle MOSI being low with the clock steady is DEAD WRONG and now you are trying to manhandle a properly behaving SPI interface to accomodate that.

GET THE ASIC FIXED and stop fooling with it.

Erik