Problem type - ADC readings excess uncertainty when reading internal reference (channel 17) - got to this point after excess ADC reading uncertainty on device pins, trying to isolate cause.
Hardware Details - small 2-layer board (about the size of a LQFP48/DIP adapter module), VSS and VSSA (4 places) to ground within a few mm, VDD and VDDA (4 places) each with 0.1 uF 0805 decoupling cap within a few mm, then on to 3.3V power source. Reset is pulled up (47K) to 3.3V power source. PA14/PA15 tied to STLINK device (STLINK device is not providing power to the target.) BOOT0 tied to 3.3V source. All other pins open.
Software details - bare-metal configuration of CPU - 24 MHz CPU clock (RC, not crystal)
// Initialize
if ((ADC1->CR2 & ADC_CR2_ADON) == 0) // ADC not turned on, so initialize
{
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // Turn on ADC1 clock
ADC1->CR2 = 0x00800001; // Turn on Vref, Temp and ADC itself
for (uint16_t volatile i = 0; i < 10000; i++); // Delay after turn-on
ADC1->CR2 = 0x00800005; // Turn on CAL, keep Vref, Temp and ADC itself on
while ((ADC1->CR2 & ADC_CR2_CAL) != 0); // Wait cal complete
ADC1->SMPR1 = (7 << ADC_SMPR1_SMP17_Pos) | (7 << ADC_SMPR1_SMP16_Pos); // ADC 16, 17 set to 239.5 cycle sample time)
ADC1->SMPR2 = 0x3FFFFFFF; // ADC 0..9 set to 239.5 cycle sample time
}
// Single read from channel 17 (reference voltage)
ADC1->SQR3 = 17; // Read reference voltage
ADC1->CR2 |= ADC_CR2_ADON; // Start conversion
while ((ADC1->SR & ADC_SR_EOC) == 0); // Wait end of conversion
uint16_t adcsample = ADC1->DR;
Observation - readings are scattered over about +/- 10 counts.
Is this indicating that VDDA (which is currently tied to VDD_1, VDD_2 and VDD_3) is encountering noise?
Happy to provide any clarifications or improvements to problem statement.
Thank you.
