stm32f103 clock (RCC) problem

[mandamahesh07]

Posted on February 05, 2015 at 12:42

Hi all,

i'm working on 103 MCU. first step is to bring up the 72Mhz clock.problem is i'm able to get clock upto 64Mhz (tested with systick),but when i configure pll mul factor to 9 control is moving to default handler while loop in startup.c file.crystal freq = 8Mhz that is input frequency.so wat's the problem.can anyone help me. #clock

[Danish1]

Posted on February 05, 2015 at 13:36

One possibility is that you haven't correctly configured the number of wait states for the FLASH memory.

It is also worth checking if the pll is taking too long to lock for 72 MHz.We could check for other possibilities if you post your code.Hope this helps,Danish

[mandamahesh07]

Posted on February 05, 2015 at 14:06 Rcc_ClockConfig( ST_RCC_ClkConfigParams_t *p_stfClkConfig){ EN_RCC_STATUS_t en_lResult = RCC_SUCCESS; INT32U u32_lHSEStatus = 0; INT32U u32_lCounter = 0; INT32U u32_lClkFreq; u32_lClkFreq = p_stfClkConfig->u8_mFreqSelect; /* Reset RCC clock to default HSI */ p_stgRccRegs->RCC_CR |= RCC_HSI_ON_MASK; /* wait for hsi ready */ while( !( p_stgRccRegs->RCC_CR & RCC_HSI_RDY_MASK )); /* reset cfgr register */ p_stgRccRegs->RCC_CFGR = 0x000000; /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ p_stgRccRegs->RCC_CFGR &= (INT32U)0xF8FF0000; /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE */ p_stgRccRegs->RCC_CFGR &= (INT32U)0xFF80FFFF; /* reset HSE_ON,PLL_ON and CSS_ON bits */ p_stgRccRegs->RCC_CR &= (INT32U)0xFEF6FFFF; /*Reset HSE_BYP bit */ p_stgRccRegs->RCC_CR &= (INT32U)0xFFFBFFFF; /* Disable all interrupts */ p_stgRccRegs->RCC_CIR = 0x009F0000;; /* Enable HSE */ p_stgRccRegs->RCC_CR |= RCC_CR_HSE_MASK; /*wait for HSE ready */ do { u32_lHSEStatus = (INT32U)( p_stgRccRegs->RCC_CR & RCC_CR_HSERDY_MASK); u32_lCounter = u32_lCounter + 1; }while( (0 == u32_lHSEStatus)&( u32_lCounter != 0x0500) );  if((p_stgRccRegs->RCC_CR & RCC_CR_HSERDY_MASK) != 0)  {  u32_lHSEStatus = (INT32U)0x01;  }  else  {  u32_lHSEStatus = (INT32U)0x00;  }  if( p_stfClkConfig->en_mSysClk == RCC_SYSCLKSRC_PLL ) { if( 2 == RCC_SYSCLKSRC_PLL) { /* configure PLL */ if( 0x01 == u32_lHSEStatus ) { p_stgRccRegs->RCC_CFGR |= (INT32U)(( PLL_HSE_SELECT << 16)| RCC_PLLMUL_3 ); /* SWITCH on main pll */ p_stgRccRegs->RCC_CR |= RCC_CR_PLLON_MASK; /* wait until pll is ready */ while(( p_stgRccRegs->RCC_CR & RCC_CR_PLLRDY_MASK ) == 0); } } }  /* configure system clock source as PLL */  p_stgRccRegs->RCC_CFGR &= ~( RCC_CFGR_SWS_WRITE_MASK );  p_stgRccRegs->RCC_CFGR |=  ( p_stfClkConfig->en_mSysClk & RCC_CFGR_SWS_WRITE_MASK);  /* check the  status of sysclock source */  while(!((p_stgRccRegs->RCC_CFGR & RCC_CFGR_SWS_READ_MASK) >> 2) \                  == p_stfClkConfig->en_mSysClk);  /*  Configure the AHB Clock as per the User Requirement - 72MHZ */  p_stgRccRegs->RCC_CFGR &= ~(RCC_CFGR_HPRE);  /* no prescaler for AHB ->72MHZ */  p_stgRccRegs->RCC_CFGR |= AHBPrescTable[((p_stgRccRegs->RCC_CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_OFFSET)];  /* Configure the APB1 bus Frequency by Dividing the AHB Clock  ->36MHZ*/  p_stgRccRegs->RCC_CFGR &= ~(RCC_CFGR_PPRE1);  p_stgRccRegs->RCC_CFGR |= (p_stfClkConfig->en_mAPB1ClkDiv << RCC_CFGR_APB1_OFFSET); /* Configure the APB2 Frequency by Divding the AHB Clock frequency = 72MHZ*/  p_stgRccRegs->RCC_CFGR &= ~(RCC_CFGR_PPRE2);  p_stgRccRegs->RCC_CFGR |= ( p_stfClkConfig->en_mAPB2ClkDiv << RCC_CFGR_APB2_OFFSET);  /* Configouring the High Speed Extenal Oscillator */  p_stgRccRegs->RCC_CR |= RCC_CR_HSE_MASK;  while(!(p_stgRccRegs->RCC_CR & RCC_CR_HSERDY_MASK));  return en_lResult;}

[Tesla DeLorean]

Posted on February 05, 2015 at 14:26

so wat's the problem.

#flashwaitstates Need correct APB clocks and FLASH settings before switching to faster clock. You know there is working example code in the firmware library...