Posted on February 16, 2016 at 15:57I am working with an STM32F103RC and trying to develop an I2C master application. Currently the I2C bus is populated with only this master and an MCP23017 slave.
In my most recent test run the program eventually ended up in a locked loop waiting for SB to set in SR1. The START bit is set, PE is set, the peripheral clock is enabled, both signals are in the passive state... how is this possible? Is there a known (yet unpublished) bug in this peripheral which would allow this condition? The obvious answer is ''yes'' unless I'm missing something.
I realize the prudent thing to do would be to have a timeout test on this wait, but why?
