STM32F072 SPI bidirectional mode strange behavior

[Kraal]

Posted on December 13, 2016 at 10:37

Hello,

I'm using the STM32F072-Nucleo64 board, and direct register access (no SPL and no HAL).

Using SPI in normal (aka full duplex) works without any problem, sending a byte is OK and receiving also is OK. But I would like to use the SPI in bidirectional mode to reuse the MISO pin (as I'm the master here) as a GPIO. Did all the register configuration according to the reference manual, but I can't switch transmission direction on the fly.

If BIDIMODE and BIDIOE are both set to 1 (MSTR also), then the clock is generated as soon as I load the DR register (which is the expected behavior). However, I would like to change direction after sending a byte to receive data from the slave. So I clear BIDIOE bit in CR1, and wait for RXNE to be set. However, the clock signal is not generated, and thus RXNE is never set.

If I set only BIDIMODE before enabling SPI, then the clock is generated continuously (as the RM says).

My question is the following: do I have to disable the SPI if I want to change transfer direction ?

Best regards,

Carl

[Kraal]

Posted on December 16, 2016 at 16:59

So I have made a good progress on this. The devil is in the details (as always), but here I'm not sure if the details were known (aka indicated in the datasheet / RM).

I wanted to initialize my SPI in half-duplex mode, master and with the ouput enabled, i.e. MOSI really is Master Out.

The following would not work:

SPI1->CR1 = SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_LSBFIRST | SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0 | SPI_CR1_MSTR | SPI_CR1_CPOL | SPI_CR1_CPHA; SPI1->CR2 = SPI_CR2_FRXTH | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; SPI1-> CR1 |= SPI_CR1_SPE;

(I really miss the code formatting)

Here I'm setting BIDIMODE and BIDIOE at the same time. As a result, in my main loop, as soon as I changed the direction of MOSI by clearing BIDIOE, the clock generation would stop and my code was stuck waiting for RXNE to be set.

BUT if I set BIDIOE not at the same time as BIDIMODE, but rather at SPI1.CR1 |= SPI_CR1_SPE | SPI_CR1_BIDIOE; then everything would work as expected...

[Kraal]

Posted on December 20, 2016 at 14:46

Ok, so further testings show that this strange behavior is only seen for the first SPI enable (after reset). If later on you disable the SPI by clearing the SPE bit, do some stuff and then set the SPE bit again, it will not stop generate clock in MISO mode. Which is good. Because I've discovered another bug.

Now my SPI is configured as half-duplex master in transmit mode. I transmit everything I want, sometimes I receive stuff if needed,no problems. Then I disable the SPI by clearing the SPE bit.

At this point nothing is wrong, except that the SCK line level is half VCC (configured as AF corresponding to the selected SPI, of course).

Remember the BIDIOE bit is still set. If you clear that BIDIOE bit, then the clock line will generate a pulse train corresponding to the data size, although the SPI was previously disabled.

So be aware of that if generating spurious clock signal is not wanted in your setup.

If anybody from ST could confirm this, it would be great.