STM32F030: Combining/modulating two PWM signals (logical AND) into one output

[Hatte]

I have a requirement to generate two PWM signals on an STMF030 MCU

• PWM1: 3-5kHz, 40-60% duty cycle
• PWM2: >40kHz, 1-100% duty cycle

I need to combine these two PWM signals, using logic AND, into one (modulated) PWM output, like so:

The signals could be combined, by:

1. Using (external) hardware to combine PWM1 and PWM2, using an AND gate or dual open collector/-drain output.
2. Configuring PWM1 to generate interrupts on rising and falling edges, and switching PWM2 on and off (x%/0%) in the ISR. PWM2 would generate the desired output.

Is it possible to perform the logic AND of the two PWM signals within the STM32 hardware/timers itself, without wasting cycles and power by having to service up to 10,000 interrupts/second?

The application is VERY cost sensitive, so changing to a more powerful STM32 range is not really an option. I might even attempt to shoehorn the final firmware into an STM8 in the end, but that would obviously be incompatible in this regard.

Any suggestions/ideas are welcome, and the solution can be hardware unique, i.e. not be HAL compatible.

/Morten

[berendi]

The output of a (master) timer can be used to start and stop the counter of a (slave) timer. This is called gated mode.

Check the SMCR register descriptions for each timer in the reference manual (TIMx internal trigger connection tables) first, to see which timer can be master to which slave.

Configure both timers with the required frequencies, and one of their channels each with the respective duty cycle. The master should generate the low frequency signal, and the slave timer the high frequency signal.

Set the MMS bits in CR2 of the master timer to the OCxREF of the channel which is generating the low frequency signal.

Set the TS bits in the SMCR register of the slave timer to select the ITRx signal which is connected to the master, and the SMS bits to gated mode.

Enable both timers (TIM_CR1_CEN).

Note the difference, as this is not exactly a logical AND combination, but the counter of the slave is stopped whenever the master output goes low. So the duty cycle of the master should be an exact multiple of the period of the slave, otherwise their phase will drift away, and the slave output will eventually be stuck high.

[Tesla DeLorean]

Could perhaps generate exotic patterns via a memory based pattern buffer, ie TIM+DMA+GPIO

[waclawek.jan]

The 'F0 have a NAND built in, between two timer channel outputs, they call it IRTIM, see the respective chapter in RM.

Being NAND, the waveform is different though.

JW

[Hatte]

Thanks, being a NAND is no problem – I can easily compensate by inverting the generated waveform.

[Hatte]

Thank you very much for pointing me in the right direction.

I have just recently started designing and writing code for the STM32 family, and the timer capabilities are quite complex. Furthermore, Google wasn't much help, as I was unable to figure out the right search terms, to lead me to the relevant information.

The frequency of the "fast" (PWM2) timer is not at all critical, so I can easily keep them synchronized. But thanks for the heads-up 🙂

[berendi]

Your welcome. By the way, STM8 has an almost identical gated mode timer feature.

[waclawek.jan]

I don't think so, that's why I mentioned it.

JW