STM3237x comparator base address?

[dhaselwood]

Posted on October 06, 2012 at 04:47

I haven't been able to find the base address for the comparator peripheral in the datasheet September 2012,(Doc ID 022691 Rev 2).  I presume it goes into one of those ''reserved'' addresses, but didn't get added to the list.  I tried to find it by working back through the std peripheral library but got lost.

[Tesla DeLorean]

Posted on October 08, 2012 at 05:20

Where APB2PERIPH_BASE = 0x40010000

#define COMP_BASE (APB2PERIPH_BASE + 0x0000001C)
#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
#define OPAMP_BASE (APB2PERIPH_BASE + 0x00000038)
#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)

[lowpowermcu]

Posted on October 08, 2012 at 10:50

Hi don,

You can find in the ST standard library: COMP is an APB2 peripheral: /*!< APB2 peripherals */ #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000) #define COMP_BASE             (APB2PERIPH_BASE + 0x001C)MCU Lüfter

[dhaselwood]

Posted on October 08, 2012 at 19:15

clive1 & lowpowermcu,

Thanks.  My latest guess was that it would be in the syscfg area based on the block diagram in the ref manual (RM0313,p11, fig 1) that shows a ''double arrow'' from the syscfg to the comp, plus the next free address for the register boundary address is 0x1c in the syscfg.  However, it is not clear if COMP is an APB1 or APB2 peripheral.  The section in the ref manual on COMP (p 276) says that the COMP is clocked by the APB1 bus.  It could be a case the designer found it most convenient place register address in the SYSCFG even though the hardware clocking is off of APB1. BTW, just where did you find that address?  I've looked through the std peripheral library that I downloaded for the F3 and I don't find it.  (I do bare metal with gcc so about all I use the std peripheral library for is to (try) to confirm what is not clear in the docs.) Don

[Tesla DeLorean]

Posted on October 08, 2012 at 20:17

\STM32F3-Discovery_FW_V1.1.0\Libraries\CMSIS\Device\ST\STM32F30x\Include\stm32f30x.h

STM32F37x_DSP_StdPeriph_Lib_V1.0.0\Libraries\CMSIS\Device\ST\STM32F37x\Include\stm32f37x.h /*!< APB2 peripherals */ #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000) #define COMP_BASE             (APB2PERIPH_BASE + 0x001C) #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400) #define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

[dhaselwood]

Posted on October 09, 2012 at 23:17

clive1,

Thanks.  I had missed that file.  However, it now raises another inconsistency.  Here is what I got out of the stm32f37x.h-- #define PERIPH_BASE           ((uint32_t)0x40000000) ... /*!< Peripheral memory map */ #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000) ... /*!< APB2 peripherals */ #define COMP_BASE             (APB2PERIPH_BASE + 0x001C) Which would have the COMP address as 0x4001001C.  However, ST is saying something different-- Dear User, Please find here below latest information concerning the request R1240591953247667 Hello, Thanks you for pointing out this missing information.  It will be corrected in the next revision.  The COMP base address is 0x4000 7C00. Regards, ST MCU Online Support 0x40007C is one of the reserved areas as shown on the datasheet, so it appears that is where ST placed COMP.   It also indicates that it is a APB1 ''sort-of'' peripheral, which is consistent with the Ref Manual that says that the COMP logic is synchronous with APB1.  It is a ''sort of'' peripheral since there is no enabling of the clocking. For me, the bottom-line is that this narrows it down so that when I get hardware going finding the correct address should be easy. Don