STM3220G_Eval SDIO/DMA Multi_block Transfer

[rmpresto]

Posted on August 02, 2011 at 19:29

Hello,

I have the STM3220G_Eval board that has the STM32F207IG processor.  I have successfully ran the demo code for transferring data to and from the SD card in Single and Multi_Block mode.  

For my application I need to write data to the card using Multi_Block; However I ''First'' need to set up all the registers, enable the DMA Stream and keep it open.  The data should be sent to the card as soon as a buffer with a size of 512 bytes is filled.  I need to also manually close the DMA stream after a timeout or other events that occur.

After reading through the reference manual and running the original program, it seems as if the Data has to be ready before the DMA stream is Enabled.  There is a counter SDIO_DCOUNT that decrements as data is transferred and fires an Transfer Complete when all the data has been transferred.  I am not sure if what I am trying to accomplish is applicable to how the DMA and SDIO drivers are set up for the STM32F207Ig.  

If there are any question to clarify my problem feel free to ask.  

Thanks in advance for your help. 

#stm32f207ig #sdio #dma

[Tesla DeLorean]

Posted on August 02, 2011 at 21:07

Well you'll definitely want the data to be present before you start the DMA transfer, otherwise you'll have the potential for race-conditions where you write junk and can't detect it. Playing catch up with DMA transfers only works for audio, and where the user can/will tolerate glitches.

You might be able to fracture the DMA into 512-byte bursts to satisfy the multi-block transfer, but if you abort mid way through the multi-block, none of the data might get to the media.

[rmpresto]

Posted on August 02, 2011 at 21:26

My goal is to write 512 bytes or a block of data to the SD card at a time until I signal the ''end transmission''   to the SD card (sort of how the multi_block is implemented).  I dont understand how their implementation of SDIO driver is  useful for real time systems.  The data is not always going to be ready for transfer, and it seems ridiculous to keep having to enable and disable the transmission when there is data to be sent.  

[Tesla DeLorean]

Posted on August 02, 2011 at 21:48

Mass storage devices work only with whole blocks of data, and care little that you haven't assembled one.

You'll need to create a level of abstraction that blocks/deblocks to the storage medium. You might be able to do this with a thread or state-machine implementation, I wouldn't expect free example code that demonstrate basic operation to be remotely sophisticated. It's why vendors make money selling more considered solutions. Like I said, you might be able to throttle the transfer into smaller units, and stall it that way. Short of enabling/disabling DMA, how would you propose to communicate your progress to hardware that is expecting service?

[rmpresto]

Posted on August 02, 2011 at 22:57

I dont really know if my problem is more on the DMA or on the SDIO side.  To answer your question I would like to fill the DMA FIFO and transmit once it is filled.

It seems to me, and I think this is your point as well, That the DMA is not going to care if the FIFO has data or not. Once it is enabled, it is just going to stream and send junk, or trigger FIFO underflow errors and such.  

However, I dont know if my problem is with the DMA as much as it is with the SDIO. 

Looking at the DPSM for SDIO I would like to stay in the Wait_S and only go to Idle when I trigger the ''End of Data''. This will be triggered under predefined events and will wait until the last block has been transferred. 

I tried to ''trick the SDIO DLEN'' Reg to 0x01FFFFFF to think that there is more data to send so it does stay in the wait state... Didnt work,  I send two blocks of data and the counter continued to run.  

I have been reading about circular buffer mode and Double buffer mode For the DMA and I am not sure if this would help.  Also Under Flow Controller in the RM: 

''The peripheral source or destination: this is the case when the number of data items to be transferred is unknown. The peripheral indicates by hardware to the DMA controller when the last data are being transferred. This feature is only supported for peripherals which are able to signal the end of the transfer, that is: - SDIO''

this is one of the problems I'm going to have because I will not know the number of data to be transferred.  But I will know when to stop the transfer based on pre-defined parameters that are manually set.  

Unfortunately, in the STM Errata: 

When HW Flow Control is enabled by setting bit 14 of SDIO_CLKCR register, some glitches can occur on the SDIO_CK output clock resulting in wrong data being written in the SD/MMC Card or the SDIO device. As consequence a data CRC error is reported to the SD/SDIO MMC host interface (DCRCFAIL bit in the SDIO_STA register is set).

Workaround None. HW Flow Control must not be used. Software has to manage Overrun Errors (Rx mode) and FIFO underrun (Tx mode).

There are soo many different configurations for the DMA,  I'm unsure which ones would need to be changed and if changing any of the configurations would even help.

Like I said before, I don't even know if what I want to do is applicable. And I am out of ideas.  

[rmpresto]

Posted on August 02, 2011 at 23:27

How about this, Is it possible to close the DMA but keep the SDIO_D write block open?  Because, I dont think I can really do anything with the DMA.